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參數(shù)資料
| 型號： | 23710 |
| 英文描述： | Understanding Burst Mode Flash Memory Devices |
| 中文描述： | 理解突發(fā)模式閃存設(shè)備 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大小： | 78K |
| 代理商： | 23710 |
Publication#
23710
Issue Date:
March 23, 2000
Rev:
A
Amendment/
0
Understanding Burst Mode Flash Memory
Devices
Application Note
Current AMD flash memory products operate with ran-
dom access times ranging from 45 ns to 150 ns, though
the most common applications are those using random
access times of about 70 to 90 ns. The faster access
times of 45 ns to 55 ns are only available today in lower
density devices from 1 to 4 Mbits.
New applications increasingly need higher speed ac-
cess, greater density, and lower voltages. However,
higher density and lower voltage tend to reduce perfor-
mance in a standard random access memory architec-
ture. To achieve faster access times, architectural
approaches such burst mode have been developed.
This application note applies to the following AMD de-
vices: Am29BL162C (16Mb) and Am29BL802C (8 Mb).
WHY USE A BURST MODE PART
burst mode devices offer improvements in system
speed and performance by reducing sequential read
access times. The burst read capability offers an aver-
age access time reduction of more than 65 percent for
an eight-word sequential read at 40 MHz. In the nor-
mal asynchronous mode, the read access time is 65 ns
per byte. For a burst mode operation, the initial access
time is also 65 ns, followed by sequential byte transfers
of 18 ns each.
REQUIRED CONTROL PINS FOR BURST
OPERATIONS
AMD burst mode devices require four extra control pins
to operate.
Load burst Address (LBA#)
LBA# indicates that the valid address is present on the
address inputs.
LBA#Lowat the rising edge of the clock latches the ad-
dress on the address inputs into the burst mode flash
device. Data becomes available t
IACC
after the rising
edge of the same clock that latches the address.
LBA# Highindicates that the address is not valid.
Burst Address Advance (BAA#)
BAA# increments the address during the burst mode
operation.
BAA# Lowenables the burst mode flash device to read
from the next word when gated with the rising edge of
the clock. Data becomes available t
BACC
ns of burst ac-
cess time after the rising edge of the clock.
BAA# High prevents the rising edge of the clock from
advancing the data to the next word output. The output
data remains unchanged.
End of Burst Indicator (IND#)
IND# Low indicates when the last word in the burst se-
quence is at the data outputs.
Clock (CLK)
Clock input that can be tied to the system or micropro-
cessor clock and provides the fundamental timing and
internal operating frequency.
CLK latches input addresses in conjunction with LBA#
input and increments the burst address with the BAA#
input.
This implementation allows easy interface with minimal
glue logic to a wide range of microprocessors/micro-
controllers for high performance read operations.
HOW DOES BURST MODE READ WORK
AMD burst mode devices have two different read
modes: random read and burst mode read.
Random Read (Non-Burst Mode Read)
Random read is an asynchronous operation, and is
how data is normally read from a standard flash mem-
ory device. A valid address must be placed on the ad-
dress lines, and both CE# and OE# must be driven to
V
IL
The valid data will be available on the data bus after
a delay of t
ACC
.
Burst Mode Read
Burst mode read is a synchronous operation that is tied
to the rising edge of a clock. The microprocessor/mi-
crocontroller supplies onlythe initial address to the de-
vice. In the linear mode, the device delivers a
continuous sequential word stream starting at the
specified word and wraps around when the end of the
internal 5 bit address counter is reached (11111). For
example, if the initial address is xxxx0h, the data is 0-
1-2-3…28-29-30-31-0-1…; if the initial address is
xxxx2h, the data order is 2-3-4-5…28-29-30-31-0-1-2-
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