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參數資料
| 型號： | 22277 |
| 英文描述： | Interfacing the Am29PL160 to the Motorola Coldfire? Processor |
| 中文描述： | 接口的Am29PL160的摩托羅拉Coldfire？處理器 |
| 文件頁數： | 8/11頁 |
| 文件大小： | 150K |
| 代理商： | 22277 |
8-14
Interfacing the Am29PL160 to the Motorola Coldfire
Processor
-- Calc the iAWS signal based
on input control signals
iAWS <= (pmcOE
or
pmcCS
or
(
not
pmcRW));
end process
;
end
Structural;
-- end code
Simulation of the Page Mode Controller
Simulation of the PMC was performed using the VSS
tool from Synopsys. The input clock frequency was set
to 33 MHz, and simulated bus cycles are applied to the
PMC to test the TA output signal. The results of the
simulation are shown in Figure 4.
Figure 4.
Simulation Results
The simulation results in Figure 4 show four separate
events. The first valid Flash access (a valid flash ac-
cess is described by the conditions CS low, RW high,
OE low, and an address on the address lines) occurs at
T1 (120 ns). The TA signal is then asserted 3 wait
states (or 3 rising clock edges) after event T1. Event
T2 (at time 330 ns) shows another Flash access of the
same page (0x1FBBF). Since this access falls within
the same page, the TA signal is asserted low after one
wait state (or 1 rising clock edge) after event T2. Event
T3 is the same as event T2, only it occurs at time 480
ns.
Event T4 shows the next Flash access, but this time to a dif-
ferent page (0x1FB8F). Since this is a page miss, the TA
signal is asserted after 3 wait states (or 3 rising clock edges).
Of important note is the assertion of the RESET signal
prior to the initial access of the Flash device. It is im-
portant to assert this signal for at least one clock period
prior to the first Flash access, to ensure that all flip-flip
storage elements are cleared to predetermined states
(so that the Address Comparator latches are cleared to
zeroes, and the initial state of the Wait State Generator
is Waiting).
Test Bench Source Code
The following text shows the VHDL source for the test
bench used to generate the simulation in Figure 4.
-- Test Bench for Page Mode Con-
troller
-- Copyright AMD 1998
library
ieee, std;
use
std.textio.all;
use
ieee.std_logic_1164.all;
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