
3.0 Volt-only Page Mode Technology Background
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masked ROMs in the 44-pin SO package. In this scenario, a system designer will be able to
use flash in the system while the code is still in development, and update the code as often as
necessary with no time or cost impact. At the point where the code is determined to be stable,
and no longer needs to be changed, a masked ROM may be dropped into the socket in place of
the Am29PL160C, and the cost benefit of masked ROMs can then be realized. The
combination of the flexibility of flash and the cost-savings of masked ROM can most
optimally be realized with the Am29PL160C device.
The page mode device can also be used for pure performance advantage as well. This device
offers initial access times as low as 65 ns, and page accesses as fast as 25 ns. In some cases,
this may result in additional cost savings by reducing the amount of DRAM required in the
system. In a typical embedded application, the memory system may contain DRAM for code
execution and Flash for control code storage. Because of faster read access times of DRAM,
the control code is typically downloaded from the flash into the DRAM and executed from
there. The fast read access times of the Am29PL160C allows shadow DRAM to be eliminated
in many cases. The code can be executed directly from the flash memory. The overall system
cost is lowered because the redundant DRAM is eliminated.
In addition, many of today’s systems still use mixed voltages. This is partly due to some 5.0 V
devices such as ASICs, processors, etc. that must be used on the board. As these devices often
control the system data and address buses, the system bus must operate at 5.0 volts. In order
to interface these buses to a lower-voltage memory devices, voltage translators must be
designed into the system to translate the higher system bus voltage down to the lower voltage
tolerated by the memory device. Because the Am29PL160C has 5 volt I/O and control signal
tolerance, DC-to-DC converters are no longer required. This leads to lower overall system
cost.
Block Diagram
Internally, the Am29PL160C is designed with the same leading-edge design as the traditional
29LVxxx family of devices, with some additional read control logic. This read control logic
was modified to allow the flash device to have 25 ns page access times. This additional logic is
incorporated into the Data Latch block in the block diagram below.