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參數(shù)資料
| 型號： | 21928 |
| 英文描述： | Low-Frequency, Spread-Spectrum EconOscillator |
| 中文描述： | 的AMD - K6 - 2E處理器數(shù)據(jù)手冊3DNow??？技術(shù)手冊 |
| 文件頁數(shù)： | 49/72頁 |
| 文件大小： | 845K |
| 代理商： | 21928 |
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Chapter 2
3DNow! Instruction Set
39
21928G/0—March 2000
3DNow! Technology Manual
PFRCP
mnemonic
opcode/imm8
description
PFRCP mmreg1, mmreg2/mem64
0Fh 0Fh / 96h
Floating-point reciprocal approximation
Privilege:
Registers Affected:
Flags Affected:
Exceptions Generated:
none
MMX
none
PFRCP is a scalar instruction that returns a low-precision estimate of the reciprocal of
the source operand. The single result value is duplicated in both high and low halves
of this instruction’s 64-bit result. The source operand is single-precision with a 24-bit
significand, and the result is accurate to 14 bits. Table 14 on page 40 shows the
numerical range of the PFRCP instruction.
Increased accuracy (the full 24 bits of a single-precision significand) requires the use
of two additional instructions (PFRCPIT1 and PFRCPIT2). The first stage of this
increase or refinement in accuracy (PFRCPIT1) requires that the input and output of
the already executed PFRCP instruction be used as input to the PFRCPIT1
instruction. Refer to “Division and Square Root” on page 59 for an
application-specific example of how to use this instruction and related instructions.
The PFRCP instruction performs the following operations:
mmreg1[31:0] = reciprocal(mmreg2/mem64[31:0])
mmreg1[63:32] = reciprocal(mmreg2/mem64[31:0])
Exception
Invalid opcode (6)
Device not available (7)
Real
X
X
Virtual
8086
X
X
Protected Description
X
X
The emulate instruction bit (EM) of the control register (CR0) is set to 1.
Save the floating-point or MMX state if the task switch bit (TS) of the control
register (CR0) is set to 1.
During instruction execution, the stack segment limit was exceeded.
During instruction execution, the effective address of one of the segment
registers used for the operand points to an illegal memory location.
One of the instruction data operands falls outside the address range 00000h
to 0FFFFh.
A page fault resulted from the execution of the instruction.
An exception is pending due to the floating-point execution unit.
Stack exception (12)
General protection (13)
X
X
Segment overrun (13)
X
X
Page fault (14)
Floating-point exception
pending (16)
Alignment check (17)
X
X
X
X
X
X
X
An unaligned memory reference resulted from the instruction execution,
and the alignment mask bit (AM) of the control register (CR0) is set to 1.
(In Protected Mode, CPL = 3.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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