參數(shù)資料
型號： 2182LPSTJ
英文描述： Interface IC
中文描述： 接口IC
文件頁數(shù)： 4/5頁
文件大小： 89K
代理商： 2182LPSTJ
4
Troubleshooting Micro Power Off Mode on élan
TM
SC300/élanSC310 Microcontrollers and Evaluation Boards
Although the élanSC300 microcontroller data sheet
and programmer’s reference manual do not specify
timing requirements necessary before asserting
IORESET and going into Micro Power Off mode, the
RSTDRV signal (the High True system reset output
from the élanSC300 microcontroller) should be
monitored to determine the following:
– The PLLs have stabilized.
– The CPU core has successfully exited the previ-
ous session of Micro Power Off mode.
– IORESET is not asserted again until RSTDRV
has been deasserted by the CPU (RSTDRV
stays True until IORESET deasserts High and
the PLLs are stable).
Understanding the above manifestation of the
high-current problem requires some understanding
of the way Micro Power Off mode is implemented on
the evaluation board. Refer to page D-20 (sche-
matic sheet #19) of the élanSC300 or élanSC310
microcontroller evaluation board manual.
When you are already in Micro Power Off mode and
you press the Micro Power Off button to wake up,
the following occurs:
– P5VOLT (used to generate VCC5, VCCSYS,
VCCSYS2, VCCMEM, and VCC1) is immediately
switched on (5 V).
– RSTDRV (with its I/O pin powered by VCCSYS)
goes True immediately following VCCSYS, while
an RC circuit delays IORESET from being deas-
serted for approximately 450 ms (the specifica-
tion requires 5
μ
s minimum).
The CPU core keeps its internal reset True during
Micro Power Off mode because the PLLs are nor-
mally off and the Loop Filters (LF1–LF4) are at 0 V.
Consequently, during Micro Power Off mode, RST-
DRV, which is asserted High internally, sets at what
would be a logic High (0.7 V to 0.8 V) instead of 0 V
on the output pin. When VCCSYS is re-applied, the
RSTDRV output is immediately reasserted High at
5 V. Approximately 450 ms after the 5-V power is
applied and RSTDRV is True, IORESET goes False
and LF1–LF4 are allowed to begin charging up to
their powered-on levels of between 1 V and 1.6 V.
When the LF1–LF4 power is stable and the PLLs
are also assumed to be stable, the RSTDRV signal
goes back Low (False). The élanSC300 microcon-
troller should be fully powered up and in
High-Speed mode at this time. When the Micro
Power Off mode button is pressed again, IORESET
is reasserted immediately (with RESIN held High).
Two DRAM refresh cycles later, P5VOLT will be
switched off. This causes a brief glitch on the RST-
DRV line because it attempts to go High when, si-
multaneously, IORESET is asserted and the
VCCSYS is lost to its I/O driver. There is no direct
correlation of any known problems related to this
glitch. At this point everything is again in normal
Micro Power Off mode.
In the previous scenario, the high-current failure oc-
curs on the evaluation board when the following
common event takes place:
When the Micro Power Off mode button is
pressed the second time
exactly
when RSTDRV
is going back Low, IORESET goes True again at
the same time that RSTDRV is going False from
the previous Micro Power Off mode session.
This event apparently sends conflicting information
to the internal state machine inside the élanSC300
microcontroller (that is, RSTDRV going False, al-
lowing the CPU to begin executing instructions in
High-Speed mode, and at the same time IORESET
going True, telling the CPU to go back into Micro
Power Off mode). This event also causes the glitch
on RSTDRV to occur at approximately the same
time, which may or may not be a contributing factor,
because it does not seem to cause any problems
with different timing. The only external indication of
an anomaly (other than the current consumption on
the VCC core and Analog VCC) is that the Loop Fil-
ters remain powered on to within a general approx-
imation of their normal High-Speed operating
voltage of between 1 V and 1.6 V. This indicates
that the internal PLLs are powered up and running
when they should be powered off.
The second condition in which the problem occurs
is when Micro Power Off mode is entered normally
and no high-current condition exists. If the Micro
Power Off mode button is pressed twice in less than
450 ms, then IORESET remains deasserted (due to
the 450-ms RC delay on IORESET deassertions).
Because IORESET remained asserted without in-
terruption, the élanSC300 microcontroller never
exits Micro Power Off mode, RSTDRV remains as-
serted internally, and the PLLs remain powered
down.
I
The third condition in which the problem occurs is
when you enter Micro Power Off mode normally and
then press the RESET button. While IORESET
remains Low (indicating Micro Power Off mode),
pressing the RESET button makes the RESIN
signal pulse Low. This causes the élanSC300
microcontroller to attempt to initialize itself and the
PLLs to power up, indicated by LF1–LF4 going High
immediately after RESIN goes Low. The timing for
this scenario is not an issue, assuming that enough
time has passed for the élanSC300 microcontroller
to properly enter Micro Power Off mode before the
RESET button is pressed.
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