參數(shù)資料
型號(hào)： 21440
廠商： Intel Corp.
英文描述： Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述： 多端口10/100Mb/s以太網(wǎng)控制器（多端口支持10/100Mbps以太網(wǎng)控制器）
文件頁(yè)數(shù)： 13/92頁(yè)
文件大?。?/td> 1352K
代理商： 21440
21440 Multiport 10/100Mb/s Ethernet Controller
2-1
Pinout
2
This chapter describes the 21440 pinout.
2.1
Signal Description
Table 2-1
describes the signals that the 21440 uses.
The following conventions are used in the signal names:
The following abbreviations are used in
Table 2-1
:
_l
Indicates that the pin is active low.
{i}
The i subscript appended to pin names indicates that
each port has its own pin (numbered from 0 to 7).
I
=
Input
O
=
Output
OD
=
Open Drain
I/O
=
Input/Output
Table 2-1. Signal Descriptions (Sheet 1 of 3)
Signal Name
CPU Interface
I/O
Pin Description
cs_l
I
Chip select.
This pin must be asserted to enable CPU access to the chip registers.
CPU port select.
Selects one of the 8 internal ports for register accesses.
Read strobe.
Upon assertion, the address signals cadd[9:0], cs_l, and cps[2:0] are latched by the chip.
Deassertion occurs after the read data is latched from the cdat[7:0] bus.
Write strobe.
Upon assertion, the address signals cadd[9:0], cs_l, and cps[2:0] are latched by the chip.
Deassertion must occur while the data is valid on the cdat[7:0] bus.
Ready indication.
When asserted, indicates that either data is stable on the cdat[7:0] bus during read
access or that data was latched by the chip during write access.
Address bus.
Selects one of the internal registers to be accessed.
CPU data bus.
Carries data to be written to or read from the registers.
Interrupt lines.
These signals are asserted following a variety of programmable conditions. Deassertion
occurs after reading the events that cause the interrupt, unless another interrupt is
registered meanwhile.
General reset.
Upon reset, all the registers are reset to their default values and the FIFOs are flushed.
cps[2:0]
I
crd_l
I
cwr_l
I
crdy_l
OD
cadd[9:0]
I
cdat[7:0]
I/O
cint{i}_l
OD
reset_l
I
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