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參數(shù)資料
| 型號： | 211AI01L |
| 英文描述： | LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER |
| 中文描述： | 低偏移，1至2差分至HSTL扇出緩沖器 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 166K |
| 代理商： | 211AI01L |
85211AMI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 1, 2005
6
Integrated
Circuit
Systems, Inc.
ICS85211I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
S
CHEMATIC
E
XAMPLE
Figure 2
shows a schematic example of ICS85211I-01. In this
example, the input is driven by an ICS HiPerClockS HSTL driver.
The decoupling capacitors should be physically located near
F
IGURE
2. ICS85211I-01 HSTL B
UFFER
S
CHEMATIC
E
XAMPLE
the power pin. For ICS85211I-01, the unused outputs
need to be terminated.
A
PPLICATION
I
NFORMATION
Figure 1
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
C1
0.1u
R4
50
U1
ICS85211-01
1
2
3
4
8
7
6
5
Q0
nQ1
nQ1
VDD
CLK
GND
Zo = 50 Ohm
R3
50
R1
50
Zo = 50 Ohm
1.8V
Zo = 50 Ohm
R5
50
Zo = 50 Ohm
LVHSTL
LVHSTL Driver
VDD=3.3V
HiPerClockS
R2
50
ICS
Unused
Output
Need To
Be
Terminated
R6
50
LVHSTL Input
+
-
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
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