參數(shù)資料
型號： 21145
廠商： Intel Corp.
英文描述： Phoneline/Ethernet LAN Controller(電話線/以太網(wǎng)LAN控制器)
中文描述： 電話線/以太網(wǎng)控制器（電話線/以太網(wǎng)局域網(wǎng)控制器）
文件頁數(shù)： 16/50頁
文件大?。?/td> 624K
代理商： 21145
21145
10
Preliminary
Datasheet
mii_clsn/sym_rxd<4>
I
147
118
In MII mode (CSR6<18>=1, CSR6<23>=0), this pin
functions as the collision detect. When the external
physical layer protocol (PHY) device detects a collision, it
asserts this pin.
In SYM mode (CSR6<18>=1, CSR6<23>=1), this pin
functions as receive data. This line along with the four
receive lines (sym_rxd<3:0>) provides five parallel data
lines in symbol form. This data is controlled by an external
physical layer medium-dependent (PMD) device and
should be synchronized to the sym_rclk signal.
mii_crs/sd
I
146
117
In MII mode this pin functions as the carrier sense and is
asserted by the PHY when the media is active.
In SYM mode this pin functions as the signal detect
indication. It is controlled by an external PMD device. If no
PHY device is connected to the MII/SYM port, the
mii_crs/sd pin should be tied to Vss in order to make the
link-integrity test function properly.
mii_dv
I
161
129
Data valid is asserted by an external PHY when receive
data is present on the mii_rxd lines and is deasserted at
the end of the packet. This signal should be synchronized
with the mii_rclk signal.
mii_mdc
O
166
134
MII management data clock is sourced by the 21145 to
the MII PHY device as a timing reference for the transfer
of information on the mii_mdio signal.
mii_mdio
I/O
167
135
MII management data input/output transfers control
information and status between the PHY and the 21145.
This signal should be tied to an external pullup resistor if
an MII PHY is connected, and to an external pulldown
resistor otherwise.
mii/sym_rclk
I
160
128
Supports either the 25-MHz or 2.5-MHz receive clock.
This clock is recovered by the PHY.
mii_rx_err/sel10_100
I/O
159
127
When used with an MII PHY device (CSR6<18>=1,
CSR6<23>=0), this pin functions as receive error input. It
is asserted when a data decoding error is detected by an
external PHY device. This signal is synchronized to
mii_rclk and can be asserted for a minimum of one
receive clock. When asserted during a packet reception,
it sets the cyclic redundancy check (CRC) error bit in the
receive descriptor (RDES0).
When used with a SYM PHY device (CSR6<23>=1), this
pin functions as select 10/100 output. The signal
sel10_100 equals 1 when the 21145 is in 100-Mb/s SYM
mode (CSR6<18>=1) and equals 0 when the 21145 is in
10BASE-T mode (CSR6<18>=0).
mii/sym_rxd<3:0>
I
162, 163,
164, 165
130,131,
132,133,
Four parallel receive data lines. This data is driven by an
external PHY that attached the media and should be
synchronized with the mii_rclk signal.
mii/sym_tclk
I
153
124
Supports the 25-MHz or 2.5-MHz transmit clock supplied
by the external PMD device. This clock should always be
active.
Table 1. Functional Description of 21145 Signals (Sheet 5 of 8)
Signal
Type
Pin
Number,
176-pin
Pin
Number,
144-pin
Description
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2-1145-89A-1 制造商: 功能描述: 制造商:undefined 功能描述:
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