
21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
2
 Brief Datasheet
Microarchitecture
The 21143 direct interface to the PCI/CardBus local bus handles all PCI/CardBus control signals 
and executes PCI/CardBus DMA and I/O transactions. The 21143 DMA dual-receive and transmit 
controller handles all data transfers between external memory and onchip memory. The controller 
communicates with the host processor by using onchip command and status registers and a shared 
host memory area. Most of the required setup and initialization is done after power-up.
The 21143 microarchitecture features large transmit and receive FIFOs, a general-purpose register, 
a full MII signal interface, and a serial ROM port. The FIFOs eliminate the need for additional 
external memory, keeping the total solution cost low. The general-purpose register enables the 
software to use input or output functions and to control LED indicators for various network 
activities.   The serial ROM port provides a direct interface to the MicroWire ROM for storage of 
Ethernet addresses and system parameters.   The CIS can also be read from the serial ROM, 
eliminating the need for an external flash ROM. 
The 21143 serial interface attachment (SIA) performs physical layer operations and implements the 
AUI and 10BASE-T functions, including the Manchester encode and decode operations. A direct 
connection to the 10BASE-T is made through the 10BASE-T port, and a direct connection to 
10BASE2 and 10BASE5 is made through the AUI port.
The 21143 implements an MII-compliant interface to 10/100-Mb/s ENDEC for 100BASE-T4 and 
100BASE-TX connections. In addition, the PCS and scrambler/descrambler function are integrated 
within the 21143, enabling operation with low-cost PHY devices, significantly reducing the cost of 
100BASE-TX solutions. 
Figure 1
 shows the functional units of the 21143 microarchitecture.
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