參數(shù)資料
型號(hào): 21084
英文描述: AMD-K6 Processor Bios Design Application Note AMD-K6 Processor I/O Model Application Note
中文描述: 的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用注意的AMD - K6處理器的I / O模型的應(yīng)用說明
文件頁數(shù): 6/14頁
文件大?。?/td> 357K
代理商: 21084
2
IBIS Modeling
AMD-K6
Processor I/O Model
21084D/0—June 1999
IBIS Modeling
Overview
IBIS is a specification developed to provide an
industry-standard method for semiconductor manufacturers to
model the analog behavior of I/O buffers without disclosing
proprietary process data. As the availability of IBIS models has
grown, so too have the number of analog simulators that accept
IBIS models.
IBIS Usage
Modeling a PCB Net
To simulate the analog behavior of a signal on a PCB net, all
elements of the net must be modeled to ensure the simulator
generates accurate results. A net that is driven by a signal that
has a short switching transition relative to its propagation delay
is best modeled as a transmission line. The general criterion
used for deciding on a transmission line as an appropriate
model is as follows:
T
switch
< 2(T
prop
)
Where:
I
T
switch
is the time required for a signal to switch states
T
prop
is the time required for a signal to propagate from its
source to its destination
I
The typical elements of a net sourced by the processor include
the processor’s I/O buffer (modeled using IBIS), the
transmission line that models the PCB trace, the destination
receiver(s), and any components used for termination (See
Figure 1). This net topology is then defined in the format
understood by the target simulator.
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