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參數(shù)資料
| 型號(hào)： | 2064VE |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | 3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| 中文描述： | 3.3在系統(tǒng)可編程高密度PLD的超快⑩ |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 200K |
| 代理商： | 2064VE |
8
Specifications
ispLSI 2064VE
ispLSI 2064VE Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
#24
20 PT
XOR Delays
Control
PTs
#33, 34,
35
I/O Pin
(Input)
Y0,1,2
GRP
#22
GLB Reg Bypass
#28
ORP Bypass
#37
D
Q
RST
RE
OE
CK
I/O Delay
#20
I/O Cell
ORP
GLB
GRP
I/O Cell
#25, 26, 27
#43, 44
#36
Reset
Ded. In
#21
#31, 32
#38,
39
GOE 0,1
#42
#40, 41
0491/2064
Comb 4 PT Bypass #23
#45
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
=
=
=
=
(0.5 + 0.6 + 2.9) + (1.2) - (0.5 + 0.6 + 1.0)
=
=
=
=
(0.5 + 0.6 + 4.0) + (1.8) - (0.5 + 0.6 + 2.9)
=
=
=
=
(0.5 + 0.6 + 4.0) + (0.3) + (1.5 + 1.5)
8.4ns
t
su
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
t
h
Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
t
co
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
Table 2-0042/2064VE
Note: Calculations are based on timing specifications for the ispLSI 2064VE-200L.
3.1ns
2.9ns
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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| 2064X | 制造商:Platt Luggage 功能描述: |
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