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參數(shù)資料
| 型號(hào)： | 2032VE |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | 3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| 中文描述： | 3.3在系統(tǒng)可編程高密度PLD的超快⑩ |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 179K |
| 代理商： | 2032VE |
Specifications
ispLSI 2032VE
11
Signal Descriptions
GOE 0
Y0
Global Output Enable Pin
Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the
device.
This pin performs two functions: (1) Dedicated clock input. This clock input is brought into the Clock
Deistribution Network and can optionally be routed to any GLB and/or I/O cell on the device. (2) Active
Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
Input
–
Dedicated in-system programming Boundary Scan Enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
Input
–
This pin performs two functions. When
BSCAN
is logic low, it functions as an input pin to load
programming data into the device. TDI/IN0 is also used as one of the two control pins for the ISP State
Machine. When
BSCAN
is high, it functions as a dedicated input pin.
Input
–
When in ISP Mode, controls operation of the ISP State Machine.
Output/Input
–
This pin performs two functions. When
BSCAN
is logic low, it functions as an output pin
pin to read serial shift register data. When
BSCAN
is high, it functions as a dedicated input pin.
Input
–
This pin performs two functions. When
BSCAN
is logic low, it functions as a clock pin for the
Serial Shift Register. When
BSCAN
is high, it functions as a dedicated clock input. This clock input is
brought into the Clock Distribution Network and can optionally be routed to any GLB and/or I/O cell on
the device.
Ground (GND)
Vcc
No Connect
Input/Output pins
–
These are the general purpose I/O pins used by the logic array.
RESET
/Y1
BSCAN
TDI/IN 0
TMS/NC
1
TDO/IN 1
TCK/Y2
GND
VCC
NC
1
I/O
Signal Name Description
GOE 0
Y0
RESET
/Y1
BSCAN
TDI/IN 0
TMS/NC
1
TDO/IN 1
TCK/Y2
GND
VCC
NC
1
40
5
29
7
8
30
18
27
17, 39
6, 28
—
2
11
35
13
14
36
24
33
1, 23
12, 34
—
43
5
31
7
8
32
19
29
18, 42
6, 30
12, 24, 36, 48
A4
C1
D7
D1
E2
C6
G4
E7
C4, E4
D3, D5
A1, A7, D4, G1, G7
Signal
44-Pin TQFP
44-Pin PLCC
48-Pin TQFP
49-Ball caBGA
1. NC pins are not to be connected to any active signals, VCC or GND.
Signal Locations
I/O Locations
Signal
44-Pin TQFP
9, 10, 11, 12, 13, 14, 15
16, 19, 20, 21, 22, 23, 24
25, 26, 31, 32, 33, 34, 35
36, 37, 38, 41, 42, 43, 44
1, 2, 3, 4
44-Pin PLCC
15, 16, 17, 18, 19, 20, 21
22, 25, 26, 27, 28, 29, 30
31, 32, 37, 38, 39, 40, 41
42, 43, 44, 3, 4, 5, 6
7, 8, 9, 10
48-Pin TQFP
49-Ball caBGA
E1, F2, F1, E3, F3, G2, F4
G3, F5, G5, F6, G6, E5, E6
F7, D6, C7, B6, B7, C5, B5
A6, B4, A5, B3, A3, B2, A2
C3, C2, B1, D2
I/O 0 - I/O 6
I/O 7 - I/O 13
I/O 14 - I/O 20
I/O 21 - I/O 27
I/O 28 - I/O 31
9, 10, 11, 13, 14, 15, 16
17, 20, 21, 22, 23, 25, 26
27, 28, 33, 34, 35, 37, 38
39, 40, 41, 44, 45, 46, 47
1, 2, 3, 4
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