參數(shù)資料
型號： 20-101-1028
廠商： Rabbit Semiconductor
文件頁數(shù)： 7/172頁
文件大小： 0K
描述： MODULE RABBITCORE RCM3750
標(biāo)準(zhǔn)包裝： 1
系列： RabbitCore®
模塊/板類型： MPU 核心模塊
適用于相關(guān)產(chǎn)品： RCM3750
產(chǎn)品目錄頁面： 619 (CN2011-ZH PDF)
其它名稱： 316-1110
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RabbitCore RCM3750
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B.1.5.3 Other A/D Converter Features
The A/D converter’s internal reference voltage is software-configurable for 1.15 V, 2.048 V,
or 2.5 V. The scaling circuitry on the Prototyping Board and the sample programs are opti-
mized for an internal reference voltage of 2.048 V. This internal reference voltage is avail-
able on pin 3 of shrouded header J8 as VREF, and allows you to convert analog input
voltages that are negative with respect to analog ground.
NOTE: The amplifier inside the A/D converter’s internal voltage reference circuit has a
very limited output-current capability. The internal buffer can source up to 20 mA and
sink only up to 20 A. A separate buffer amplifier at U7 supplies the load current.
The A/D converter’s CONVERT pin is available on pin 2 of shrouded header J8, and can
be used as a hardware means of forcing the A/D converter to start a conversion cycle. The
CONVERT signal is an edge-triggered event and has a hold time of two CCLK periods for
debounce.
A conversion is started by an active (rising) edge on the CONVERT pin. The CONVERT
pin must stay low for at least two CCLK periods before going high for at least two CCLK
periods. Figure B-7 shows the timing of a conversion start. The double falling arrow on
CCLK indicates the actual start of the conversion cycle.
Figure B-7. Timing Diagram for Conversion Start Using CONVERT Pin
CCLK
BUSY
CONV
Conversion starts
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參數(shù)描述
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