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參數(shù)資料
| 型號： | 1771U |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Low-Voltage Synchronous Buck Controller with Precision Enable and No External Compensation |
| 中文描述： | 低電壓同步降壓控制器，具有高精度允許任何外部補償 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大小： | 772K |
| 代理商： | 1771U |
MOSFET Selection
(Continued)
20189034
It can be seen that the average output voltage (V
OUT_AC-
TUAL
) is higher than the output voltage (V
) that was
calculated by the earlier equation by exactly half the output
voltage ripple. The output voltage that is targeted for regu-
lation may then be appended according to the voltage ripple.
This can be seen below:
V
OUT_ACTUAL
= V
OUT_SET
+
1
2
V
OUT
= V
OUT_SET
+
1
2
I
L
x
R
ESR
Efficiency Calculations
One of the most important parameters to calculate during the
design stage is the expected efficiency of the system. This
can help determine optimal FET selection and can be used
to calculate expected temperature rise of the individual com-
ponents. The individual losses of each component are bro-
ken down and the equations are listed below:
QUIESCENT CURRENT
The quiescent current consumed by the LM1771 is one of
the major sources of loss within the controller. However, from
a system standpoint this is usually less than 0.5% of the
overall efficiency. Therefore, it could easily be omitted but is
shown for completeness:
P
IQ
= V
IN
x I
Q
CONDUCTION LOSS
There are three losses associated with the external FETs.
From the DC standpoint there is the I-squared R loss,
caused by the on resistance of the FET. This can be mod-
eled for the PMOS by:
P
P_COND
= D x R
DSON_PMOS
x I
OUT2
and the NMOS by:
P
N_COND
= (1 - D) x R
DSON_NMOS
x I
OUT2
SWITCHING LOSS
The next loss is the switching loss that is caused by the need
to charge and discharge the gate capacitance of the FETs
every cycle. This can be approximated by:
P
P_SWITCH
= V
IN
x Q
g_PMOS
x f
SW
for the PMOS, and the same approach can be adapted for
the NMOS:
P
N_SWITCH
= V
IN
x Q
g_NMOS
x f
SW
TRANSITIONAL LOSS
The last FET power loss is the transitional loss. This is
caused by switching the PMOS while it is conducting current.
This approach only models the PMOS transition, the NMOS
loss is considered negligible because it has minimal drain to
source voltage when it switches due to the conduction of the
body diode. Therefore the transitional loss of the PMOS can
be modeled by:
P
P_TRANSITIONAL
= 0.5 x V
IN
x I
OUT
x f
SW
x (t
r
+ t
f
)
t
and t
are the rise and fall times of the FET and can be
found in their corresponding datasheet. Typically these num-
bers are simulated using a 6
drive, which corresponds well
to the LM1771. Given this, no adjustment is needed.
DCR LOSS
The last source of power loss in the system that needs to be
calculated is the loss associated with the inductor resistance
(DCR) which can be calculated by:
P
DCR
= R
DCR
x I
OUT2
EFFICIENCY
The efficiency,
η
, can then be calculated by summing all the
power losses and then using the equation below:
Thermals
By breaking down the individual power loss in each compo-
nent it makes it easy to determine the temperature rise of
each component. Generally the expected temperature rise
of the LM1771 is extremely low as it is not in the power path.
Therefore the only two items of concern are the PMOS and
the NMOS. The power loss in the PMOS is the sum of the
conduction loss and transitional loss, while the NMOS only
has conduction loss. It is assumed that any loss associated
with the body diode conduction during the dead-time is
negligible.
For completeness of design it is important to watch out for
the temperature rise of the inductor.Assuming the inductor is
kept out of saturation the predominant loss will be the DC
copper resistance. At higher frequencies, depending on the
core material, the core loss could approach or exceed the
DCR losses. Consult with the inductor manufacturer for ap-
propriate temp curves based on current.
L
www.national.com
13
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