參數(shù)資料
型號(hào)： 17512LJC
廠商： Xilinx, Inc.
英文描述： Serial Configuration PROMs
中文描述： 串行配置PROM的
文件頁(yè)數(shù)： 4/10頁(yè)
文件大?。?/td> 72K
代理商： 17512LJC
XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs
5-4
December 10, 1997 (Version 1.1)
Figure 2: Master Serial Mode.
The one-time-programmable Serial Configuration PROM supports automatic loading of
configuration programs. Multiple devices can be cascaded to support additional FPGA. An early D/P inhibits the
PROM data output one CCLK cycle before the FPGA I/Os become active.
* If Readback is
Activated, a
3.3-k
Resistor is
Required in
Series With M1
During Configuration
the 3.3 k
M2 Pull-Down
Resistor Overcomes the
Internal Pull-Up,
but it Allows M2 to
be User I/O.
General-
Purpose
User I/O
Pins
Other
I/O Pins
M2
HDC
LDC
INIT
RESET
DIN
CCLK
INIT
D/P
SCP
DATA
CEO
CLK
CE
OPTIONAL
Slave FPGAs
with Identical
Configurations
Vcc
*
M0 M1 PWRDWN
FPGA
(Low Resets the Address Pointer)
Vcc
VCC
VPP
RESET
X8256
Cascaded
Serial
Memory
DATA
CLK
CE
OPTIONAL
Daisy-chained
FPGAs with
Different
Configurations
DOUT
CCLK
(OUTPUT)
DIN
DOUT
(OUTPUT)
OE/RESET
OE/RESET
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