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參數(shù)資料
| 型號： | 16F84A |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | CAT 5E CROSSOVER PATCH CORD CABLE BLUE 20 FT |
| 中文描述： | 18引腳閃存/ EEPROM的8位微控制器 |
| 文件頁數(shù)： | 35/124頁 |
| 文件大?。?/td> | 1322K |
| 代理商： | 16F84A |
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PIC16F8X
1998 Microchip Technology Inc.
DS30430C-page 35
7.5
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example 7-1) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit. The Total Endurance disk
will help determine your comfort level.
Generally the EEPROM write failure will be a bit which
was written as a '1', but reads back as a '0' (due to
leakage off the bit).
EXAMPLE 7-1:
WRITE VERIFY
BCF STATUS, RP0 ; Bank 0
: ; Any code can go here
: ;
MOVF EEDATA, W ; Must be in Bank 0
BSF STATUS, RP0 ; Bank 1
READ
BSF EECON1, RD ; YES, Read the
; value written
BCF STATUS, RP0 ; Bank 0
;
; Is the value written (in W reg) and
; read (in EEDATA) the same
;
SUBWF EEDATA, W ;
BTFSS STATUS, Z ; Is difference 0
TABLE 7-1
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
GOTO WRITE_ERR ; NO, Write error
: ; YES, Good write
: ; Continue program
7.6
Protection Against Spurious Writes
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up
Timer
(72
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
ms
duration)
prevents
7.7
Data EEPROM Operation during Code
Protect
When the device is code protected, the CPU is able to
read and write unscrambled data to the Data
EEPROM.
For ROM devices, there are two code protection bits
(Section 8.1). One for the ROM program memory and
one for the Data EEPROM memory.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
08h
EEDATA
EEPROM data register
xxxx xxxx
uuuu uuuu
09h
EEADR
EEPROM address register
xxxx xxxx
uuuu uuuu
88h
EECON1
—
—
—
EEIF
WRERR
WREN
WR
RD
---0 x000
---0 q000
89h
EECON2
EEPROM control register 2
---- ----
---- ----
Legend:
x
= unknown,
u
= unchanged,
-
= unimplemented read as '0',
q
= value depends upon condition. Shaded cells are not
used by Data EEPROM.
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