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參數(shù)資料
| 型號(hào)： | 1345TAPC |
| 英文描述： | 1345-Type Receiver with Clock Recovery and Data Retiming |
| 中文描述： | 1345型的時(shí)鐘恢復(fù)和數(shù)據(jù)重定時(shí)接收機(jī) |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 98K |
| 代理商： | 1345TAPC |
1345-Type Receiver with
Clock Recovery and Data Retiming
Data Sheet
January 2000
Operating at 1.3
μ
m or 1.55
μ
m wavelengths and at
155 Mbits/s or 622 Mbits/s, the versatile 1345-Type Receiver is
manufactured in a 20-pin, plastic DIP with a multimode fiber
pigtail.
Features
I
Backward compatible with 1330 family
I
Space-saving, self-contained, 20-pin plastic DIP
I
Silicon based ICs
I
Single 5 V power supply operation including
photocurrent monitor capability
I
Exceeds all SONET (GR-253-CORE) and ITU-T
G.958 jitter requirements
I
Clocked decision circuit
I
Regenerated differential clock signal
I
Wide dynamic range
I
Qualified to meet the intent of Telcordia Technolo-
gies
reliability practices
I
Operates at data rates of 155 Mbits/s or
622 Mbits/s
I
Positive ECL (PECL) data outputs
I
CMOS (TTL) link-status flag output
I
Operation at 1.3
μ
m or 1.55
μ
m wavelengths
I
Operating temperature range of –40 °C to +85 °C
Applications
I
Telecommunications:
— Inter- and intraoffice SONET/ITU-T SDH
— Subscriber loop
— Metropolitan area networks
I
High-speed data communications
Description
The 1345-Type fiber-optic receiver is designed for
use in transmission systems or medium- to high-
speed data communication applications. Used in
intermediate- and long-reach applications, the
receiver operates at the SONET OC-3 or OC-12 data
rate as well as the ITU-T synchronous digital hierar-
chy (SDH) rate of STM-1 or STM-4, depending on
the receiver model chosen. The receiver meets all
present Telcordia Technologies GR-253-CORE
requirements, the current ANSI T1X1.5 intraoffice
specifications, and the ITU-T G.957 and G.958 rec-
ommendations. Compact packaging, a high level of
integration, and a wide dynamic range make these
receivers ideal for data communications.
Manufactured in a 20-pin DIP the receiver consists of
a planar InGaAs PIN photodetector, a silicon pream-
plifier, a silicon bipolar limiting amplifier that converts
the small signal to ECL levels, a timing recovery unit
to recover the clock, and a silicon bipolar decision cir-
cuit.
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