
[AK4671]
MS0666-E-00
2007/10
- 145 -
SYSTEM DESIGN
Figure 108
shows the system connection diagram for the AK4671. The evaluation board [AKD4671] demonstrates the
optimum layout, power supply arrangements and measurement results.
Headphone
TEST
LOUT2
ROUT2
VCOM
VCOCBT
VSS2
SDTOA
SYNCA
GPO2
AVDD
VSS1
MUTET
VCOC
PVDD
TVDD2
BICKA
CDTI
SDTIA
RCP
RCN
VSS4
DVDD
ROUT3
LOUT3
CCLK
CSN
RIN4
LIN4
I2C
BICK
LIN3
RIN3
MCKI
MCKO
IN2+
IN2
PDN
LRCK
IN1+
IN1
SAIN2
SAVDD
TVDD3
SDTOB
BICKB
SDTO
CDTO
MDT
MPWR
SAIN3
SAIN1
VSS3
SYNCB
SDTIB
SDTI
GPO1
NC
AK4671EG
Top View
Analog
2.2
~
3.6V
1
R
C
0
2
R
C
0
0
Base Band
Digital
(Base Band)
1.6
~
3.6V
μ
P
Digital
(
μ
P & CPU)
1.6
~
3.6V
CPU
Bluetooth
Module
Digital
(Bluetooth)
1.6
~
3.6V
0.1u
0
0
0.1u
1
1
2
Receiver
Stereo
Speaker
Line In
External MIC
Internal MIC
DC Measurement
Ext SPK-Amp
Digital
Ground
Analog
Ground
10u
Notes:
- VSS1, VSS2, VSS3 and VSS4 of the AK4671 should be distributed separately from the ground of external
controllers.
- All digital input pins should not be left floating.
- When the AK4671 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of the VCOC pin is not needed.
- When the AK4671 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of the VCOC pin is shown in
Table
4
.
- When the AK4671 is used by master mode, LRCK and BICK pins are a Hi-Z state until M/S bit becomes “1”.
LRCK and BICK pins of the AK4671 should be pulled-down or pulled-up by the resistor (about 100k
Ω
)
externally to avoid the floating state.
- A resistor and capacitor of the VCOCBT pin is shown in
Table 76
.
- After setting PDN pin = “H”, the PCM I/F clock pins of AK4671 are a Hi-Z state until PMPCM bit becomes
“1”. The PCM I/F clock pins of master mode should be pulled-down or pulled-up by the resistor (about 100k
Ω
)
externally to avoid the floating state.
Figure 108. Typical Connection Diagram
(Internal Full-differentila Mic, External pseudo differential Mic, Recevier Output, 4-wire serial mode)