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參數(shù)資料
| 型號(hào)： | 11640-838 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | DUAL PLL CLOCK GENERATOR IC |
| 中文描述： | 雙PLL時(shí)鐘發(fā)生器芯片 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 51K |
| 代理商： | 11640-838 |
AMERICAN MICROSYSTEMS, INC.
October 1999
This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.
ISO9001
10.1.99
FS6282
Dual PLL Clock Generator IC
1.0 Features
Dual phase-locked loop (PLL) device with three out-
put clock frequencies
3.3V supply voltage
Small circuit board footprint (8-pin 0.150
″
SOIC)
Custom frequency selections available - contact your
local AMI Sales Representative for more information
Figure 1: Pin Configuration
1
8
2
3
4
7
6
5
CLKA
VSS
XIN
XOUT
VDD
CLKC
CLKB
OE
F
8-pin (0.150
″
) SOIC
2.0 Description
The FS6282 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video/audio systems.
Two high-resolution phase-locked loops generate two
output clocks (CLKA and CLKB) through an array of post-
dividers. All frequencies are ratiometrically derived from
the crystal oscillator frequency. The locking of all the out-
put frequencies together can eliminate unpredictable ar-
tifacts in video systems and reduce electromagnetic in-
terference (EMI) due to frequency harmonic stacking.
Table 1: Crystal / Output Frequencies
DEVICE
f
XIN
(MHz) CLKA (MHz) CLKB (MHz) CLKC (MHz)
FS6282-03
NOTE: Contact AMI for custom PLL frequencies
20.000
20.000
48.000
8.000
Figure 2: Block Diagram
CRYSTAL
OSC.
FS6282
XOUT
XIN
CLKC
CLKA
DIVIDER
ARRAY
PLL
PLL
CLKB
OE
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