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參數(shù)資料
| 型號(hào)： | 1022PE-42TE13 |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁(yè)數(shù)： | 5/17頁(yè) |
| 文件大?。?/td> | 107K |
| 代理商： | 1022PE-42TE13 |
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13
Preliminary Information
CAT1021, CAT1022, CAT1023
Doc No. 3009, Rev. E
Immediate/Current Address Read
The CAT1021/22/23 address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
access data from address N+1. For all devices, N=E=255.
The counter will wrap around to Zero and continue to
clock out valid data for the 2K devices.
After the
CAT1021/22/23 receives its slave address information
(with the R/
W bit set to one), it issues an acknowledge,
then transmits the 8-bit byte requested. The master
device does not send an acknowledge, but will generate
a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condition,
slave address and byte addresses of the location it
wishes to read. After the CAT1021/22/23 acknowledges,
the Master device sends the START condition and the
slave address again, this time with the R/
W bit set to one.
The CAT1021/22/23 then responds with its acknowledge
and sends the 8-bit byte requested. The master device
does not send an acknowledge but will generate a
STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1021/22/23 sends the inital 8-
bit byte requested, the Master will responds with an
acknowledge which tells the device it requires more
data. The CAT1021/22/23 will continue to output an 8-bit
byte for each acknowledge, thus sending the STOP
condition.
The data being transmitted from the CAT1021/22/23 is
sent sequentially with the data from address N followed
by data from address N+1. The READ operation address
counter increments all of the CAT1021/22/23 address
bits so that the entire memory array can be read during
one operation.
SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
O
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
BYTE
ADDRESS (n)
S
A
C
K
DATA n
SLAVE
ADDRESS
A
C
K
S
T
A
R
T
Figure 11. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+x
DATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
Figure 12. Sequential Read Timing
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