SRAM. Dynamic C provid" />
參數(shù)資料
型號： 101-1156
廠商： Rabbit Semiconductor
文件頁數(shù)： 87/134頁
文件大?。?/td> 0K
描述： KIT DEVELOPMENT INT'L RCM4200
標準包裝： 1
系列： RabbitCore 4000
類型： MPU 模塊
適用于相關產(chǎn)品： RCM4200
所含物品： RabbitCore 模塊、開發(fā)板、交流適配器、纜線和 Dynamic C? 光盤
50
RabbitCore RCM4200
5.2.4 SRAM Use
The RCM4200 module has a battery-backed data SRAM and a program-execution
SRAM. Dynamic C provides the protected keyword to identify variables that are to be
placed into the battery-backed SRAM. The compiler generates code that maintains two
copies of each protected variable in the battery-backed SRAM. The compiler also generates
a flag to indicate which copy of the protected variable is valid at the current time. This flag
is also stored in the battery-backed SRAM. When a protected variable is updated, the
“inactive” copy is modified, and is made “active” only when the update is 100% complete.
This assures the integrity of the data in case a reset or a power failure occurs during the
update process. At power-on the application program uses the active copy of the variable
pointed to by its associated flag.
The sample code below shows how a protected variable is defined and how its value can
be restored.
main() {
protected int state1, state2, state3;
...
_sysIsSoftReset();
// restore any protected variables
The bbram keyword may also be used instead if there is a need to store a variable in
battery-backed SRAM without affecting the performance of the application program. Data
integrity is not assured when a reset or power failure occurs during the update process.
Additional information on bbram and protected variables is available in the Dynamic C
User’s Manual.
5.2.4.1 SRAM Chip Select Considerations
The basic SRAM memory on Rabbit-based boards is always connected to /CS1, /OE1, and
/WE1. Both the data SRAM and the program execution fast SRAM on the RCM4200
share /OE1.
The BIOS-defined macro, CS1_ALWAYS_ON, is set to 0 by default to disable /CS1 (set it
high). The macro may be redefined in the BIOS to 1, which will set a bit in the MMIDR
register that forces /CS1 to stay enabled (low). This capability is normally used to speed up
access time for battery-backed SRAM as long as no other memory chips are connected to
/OE1 and /WE1. Therefore, the CS1_ALWAYS_ON macro must remain at its default setting
of 0 to avoid conflicts between the data SRAM and the program execution fast SRAM.
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