Table A-4 lists the delays in gross memory access time for VDD = " />
參數(shù)資料
型號： 101-0518
廠商： Rabbit Semiconductor
文件頁數(shù)： 52/110頁
文件大?。?/td> 0K
描述： MODULE RABBITCORE RCM3110
標準包裝： 50
系列： RabbitCore®
模塊/板類型： MPU 核心模塊
適用于相關產(chǎn)品： RCM3110
其它名稱： 316-1022
40
RabbitCore RCM3100
Table A-4 lists the delays in gross memory access time for VDD = 3.3 V.
The measurements are taken at the 50% points under the following conditions.
T = -40°C to 85°C, V = VDD ±10%
Internal clock to nonloaded CLK pin delay
≤ 1 ns @ 85°C/3.0 V
The clock to address output delays are similar, and apply to the following delays.
Tadr, the clock to address delay
TCSx, the clock to memory chip select delay
TWEx, the clock to memory write strobe delay
TIOCSx, the clock to I/O chip select delay
TIORD, the clock to I/O read strobe delay
TIOWR, the clock to I/O write strobe delay
TBUFEN, the clock to I/O buffer enable delay
The data setup time delays are similar for both Tsetup and Thold.
When the spectrum spreader is enabled with the clock doubler, every other clock cycle is
shortened (sometimes lengthened) by a maximum amount given in the table above. The
shortening takes place by shortening the high part of the clock. If the doubler is not
enabled, then every clock is shortened during the low part of the clock period. The maxi-
mum shortening for a pair of clocks combined is shown in the table.
Table A-4. Data and Clock Delays VDD ±10%, Temp, -40°C–+85°C (maximum)
VDD
Clock to Address Output Delay
(ns)
Data Setup
Time Delay
(ns)
Spectrum Spreader Delay
(ns)
30 pF
60 pF
90 pF
Normal
dbl/no dbl
Strong
dbl/no dbl
3.3
6
8
11
1
3/4.5
4.5/9
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