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參數(shù)資料
| 型號： | 10020EV8-4F |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | ECL programmable array logic |
| 中文描述： | OT PLD, 4.7 ns, CDIP24 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-24 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大小： | 140K |
| 代理商： | 10020EV8-4F |
Philips Semiconductors Programmable Logic Devices
Product specification
10H20EV8/10020EV8
ECL programmable array logic
October 22, 1993
125
REGISTER PRELOAD
The 10H20EV8/10020EV8 has included
circuitry that allows a user to load data into
the output registers. Register PRELOAD can
be done at any time and is not dependent on
any particular pattern programmed into the
device. This simplifies the ability to fully verify
logic states and sequences even after the
device has been patterned.
The pin levels and sequence necessary to
perform the register PRELOAD are shown
below.
PIN 3
PIN 23
OUTPUTS
VIH
VPP
VOH
VOL
VIL
VIH
DISABLE OUTPUTS
ENABLE PRELOAD
APPLY EXTERNAL
INPUTS TO BE
PRELOADED
DATA PRELOADED
AND PRELOAD
DISABLED
REMOVE EXTERNAL
INPUTS
LIMITS
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VIH
Input HIGH level during
PRELOAD and Verify
–1.1
–0.9
–0.7
V
VIL
Input LOW level during
PRELOAD and Verify
–1.85
–1.65
–1.45
V
VPP
PRELOAD enable voltage
applied to I11
1.45
1.6
1.75
V
NOTE:
1. Unused inputs should be handled as follows:
– Set at VIH or VIL
– Terminated to –2V
– Tied to VEE through a resistor > 10K
– Open
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