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參數(shù)資料
| 型號： | 0RTC72423B |
| 英文描述： | IC SMD |
| 中文描述： | 集成電路貼片 |
| 文件頁數(shù)： | 2/2頁 |
| 文件大?。?/td> | 107K |
| 代理商： | 0RTC72423B |
Real Time Clock Modules - Seiko Epson
1997/98 FREQUENCY CONTROL MANU AL
RTC-72421/72423 Continued
Notes
0=“L” revel, 1=“H” revel, REST=RESET ITRPT/STND=INTRUPT/STANDARD
1. Bit * does not exist
2. Please mask AM/PM bit with 10’s of hours operation
3. Busy is read only. IRQ can only be set low (“0”)
4.
Data Bit
PM/AM
ITRPT/STND
24/12
1
PM
ITRPT
24
0
AM
STND
12
Function Table
Data
Count
A3 A2 A1 A0
D3
D2
D1
D0
value
Remarks
00
0
S
1
S
8
S
4
S
2
S
1
0~9
1 second digit register
10
0
1
S
10
*S
40
S
20
S
10
0~5
10 second digit register
20
0
1
0
MI
1
mi
8
mi
4
mi
2
mi1
0~9
1 minute digit register
30
0
1
MI
10
*mi
40
mi
20
mi
10
0~5
10 minute digit register
40
1
0
0H
1
h
8
h
4
h
2
h
1
0~9
1 hour digit register
50
1
0
1H
1
*
PM/AM
h
20
h10
0~2
PM/AM, 10 hour digit register
or
0~1
60
1
0D
1
d
8
d4
d
2
d1
0~9
1 day digit register
70
1
D
10
**
d
20
d
10
0~3
10 day digit register
81
0
M0
1
mo
8
mo
4
mo
2
mo
1
0~9
1 month digit register
91
0
1 M0
10
**
*
mo
10
0~1
10 month digit register
A1
0
1
0
Y
1
y
8
y
4
y
2
y
1
0~9
1 year digit register
B1
0
1
Y
10
y
80
y
40
y
20
y
10
0~9
10 year digit register
C1
1
0
W
*
w
2
w
1
0~6
week register
D1
1
0
1 Reg D 30 sec
IRQ
BUSY
HOLD
-
Control register D
ADJ
FLAG
E1
1
0 Reg E
t1
t0
ITRPT
MASK
-
Control register E
/STND
F1
1
1 Reg F TEST
24/12
STOP
REST
-
Control register F
Ad
dr
ess
Register
Switching Characteristics (with ALE)
Please connect ALE to VDD (If the microprocessor does not have an ALE OUTPUT)
Item
Symbol
Condition
Min
Max
Unit
CS1 set up time
t
SU(CS1)
-
1000
-
nS
Address set up time
t
su(A-ALE)
-50
-
nS
Address hold time
t
h(ALE-A)
-50
-
nS
ALE pulse width
t
W(ALE)
-80
-
nS
ALE before WRITE
t
SU(ALE-W)
-0
-
nS
ALE before READ
t
SU(ALE-R)
-0
-
nS
ALE before WRITE
t
SU(W-ALE)
-50
-
nS
ALE before READ
t
SU(R-ALE)
-50
-
nS
WHITE pulse width
t
w/(w)
-
120
-
nS
RD to DATA
t
PZV(R-Q)
C
L=150pF
-
120
nS
DATA hold
t
PVZ(R-Q)
-0
-
nS
DATA setup time
t
SU(D-W)
-80
-
nS
DATA hold time
t
h(W-D)
-10
-
nS
CS1 hold time
t
h(CSI)
-
1000
-
nS
RD/WR recovery time
t
REC(R-W)
-
200
-
nS
(VDD=5V±, Ta=-1070°C)
Write Mode (with ALE)
Read Mode (with ALE)
Data Holding Timing
Block Diagram
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