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參數(shù)資料
| 型號： | 0804-5000-11 |
| 廠商： | BEL FUSE INC |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| 封裝： | ROHS COMPLIANT, PACKAGE-40 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 484K |
| 代理商： | 0804-5000-11 |
POWERLINE MODULES
Turbo SIMPLE PowerPacket Modules
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 Tel 201-432-0463 Fax 201-432-9542 www.belfuse.com
2009 Bel Fuse Inc. Specifications subject to change without notice. 07.24.09
Page 10
2.4 HOST/DTE Pin Descriptions by Group
Group
Pin Number
Signal Name
Description
I/O
HOST/DTE Option: this option is selected when MODE) is tied to VSS.
MII
10 9 8 7
MII_RXD0 MII_RXD1 MII_RXD2
MII_RXD3
MII Receive Data Data is transferred from the IC
across these four lines one nibble at a time.
I
12
MII_RXCLK
MII Receive Clock The Receive Clock is
synchronous to the incoming data and is
continuous. This clock operates at 25 MHz
(100BaseT) or 2.5 MHz (10BaseT).
I
11
MII_RXDV
MII Receive Data Valid This Signal indicates that
the data on the MII_RXD[3:0] pins are valid.
I
14
MII_RXER
MII Receive Error The MII_RXER signal indicates
that an error has occurred during frame reception.
I
20
MII_COL
MII Collision Detect The MII Collision Detect signal
indicates that a collision has been detected on the
MII interface and shall remain asserted while the
collision condition persists.
I
21 22 23 24
MII_TXD0 MII_TXD1 MII_TXD2
MII_TXD3
MII Transmit data Data is transferred to the IC
across the four lines one nibble at a time.
O
18
MII_TXCLK
MII Transmit Clock This clock operates at 25MHz
(100BaseT) or 2.5MHz (10BaseT).
I
19
MII_TXEN
MII Transmit Enable The MII Transmit Enable
signal indicates that valid data is present on the
MII_TXD[3:0] pins.
O
13
MII_CRS
MII Carrier Sense The MII Carrier Sense signal
is asserted when either the transmit or receive
medium is non-idle.
I
17
MII_TXER
MII Transmit Error Assertion of this signal causes
intentionally bad data to be transmitted.
O
28
MII_MDIO
MII Management Data Input/Output The MII_
MDIO signal is a bi-directional data pin for the
Management Data Interface (MDI).
I/O
29
MII_MDCLK
MII Management Data Clock The MII_MDCLK
signal is a clock reference for the MII_MDIO signal.
O
1
25MHz
25MHz clock to Ethernet PHY IC.
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