參數(shù)資料
型號(hào)： 0804-5000-09
廠商： BEL FUSE INC
元件分類： 電源模塊
英文描述： Embedded SIP - vertical mount
中文描述： 1-OUTPUT AC-DC REG PWR SUPPLY MODULE
封裝： ROHS COMPLIANT, PACKAGE-40
文件頁(yè)數(shù)： 12/13頁(yè)
文件大?。?/td> 484K
代理商： 0804-5000-09
POWERLINE MODULES
Turbo SIMPLE PowerPacket Modules
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 Tel 201-432-0463 Fax 201-432-9542 www.belfuse.com
2009 Bel Fuse Inc. Specifications subject to change without notice. 07.24.09
Page 8
2.2 MII PHY Pin Descriptions by Group
Group
Pin Number
Signal Name
Description
I/O
28
MII_MDIO
MII Management Data Input/Output The
MII_MDIO signal is a bi-directional data pin
for the Management Data Interface (MDI).
I/O
29
MII_MDCLK
MII Management Data Clock The MII_
MDCLK signal is a clock reference for the
MII_MDIO signal.
I
26
PHY_ADRSEL1
Address Select 0 Used to compare against
the upper two bits of MDI Address.
I
27
PHY_ADRSEL2
Address Select 1 Used to compare against
the upper two bits of MDI Address.
I
1
25MHZ
25MHZ Clock Output
O
General Groups
Control
5
LINE_SYNC
AC line zero-cross detect signal
I
16
GPIO6
The pull-up/ pull-down values is latched as
Boot Source upon power-up/ reset. Tie to
VSS for normal operation.
I/O
LEDs
34
LED1
LED Driver Output – Indicates Power Good
(default setting)
O
33
LED2
LED Driver Ouput – Indicates network link/
activity on the PL interface (default setting)
O
Reset
32
RESET_N
Resets all module logic when low
I
AFE
36 37 38 39
TX_P TX_N RX_N RX_P
Analog Transmit Output (Complimentary)
Analog Transmit Output Analog Receive Input
Analog Receive Input (Complementary)
O O I I
Power &
Ground
4,15,25,35
VSS
Ground
I
30,31
VDD
+3.3V DC with respect to VSS
I
3
VDD_C
+1.8V DC with respect to Ground
I
40
VAA
+7.5V DC with respect to Ground
I
Mode
Select
6
MODE0
Mode Select Pin Tie to VDD for PHY option.
I
NC
2
KEY
Unused
相關(guān)PDF資料
PDF描述
0804-5000-11 1-OUTPUT DC-DC REG PWR SUPPLY MODULE
935269725112 ALVC/VCX/A SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDSO20
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