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參數(shù)資料
| 型號： | 0804-5000-08 |
| 廠商： | BEL FUSE INC |
| 元件分類： | 電源模塊 |
| 英文描述： | Embedded SIP - vertical mount |
| 中文描述： | 1-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| 封裝： | ROHS COMPLIANT, PACKAGE-40 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 484K |
| 代理商： | 0804-5000-08 |
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 Tel 201-432-0463 Fax 201-432-9542 www.belfuse.com
2009 Bel Fuse Inc. Specifications subject to change without notice. 07.24.09
POWERLINE MODULES
Turbo SIMPLE PowerPacket Modules
Page 7
2.2 MII PHY Pin Descriptions by Group
Group
Pin
Number
Signal Name
Description
I/O
PHY Option: this option is selected when MODE0 is connected to VDD.
MII
10 9 8 7
MII_RXD0 MII_RXD1 MII_RXD2 MII_RXD3
MII Receive Data Data is transferred from
the IC across these four lines one nibble
at a time.
O
12
MII_RXCLK
MII Receive Clock The Receive Clock is
synchronous to the data and is continuous.
This clock operates at 25 MHz.
O
11
MII_RXDV
MII Receive Data Valid This Signal
indicates that the data on the MII_RXD[3:
0] pins are valid.
O
14
MII_RXER
MII Receive Error The MII_RXER signal
indicates that an error has occurred during
frame reception.
O
20
MII_COL
MII Collision Detect The MII Collision
Detect Signal indicates to the MAC that a
collision has occurred on the MII interface.
MII_COL is an asynchronous output
signal.
O
21 22 23 24
MII_TXD0 MII_TXD1 MII_TXD2 MII_TXD3
MII Transmit data Data is transferred to
the IC across the four lines one nibble at
a time.
I
18
MII_TXCLK
MII Transmit Clock The Transmit Clock
outputs a continuous clock. This clock
operates at 25MHz.
O
19
MII_TXEN
MII Transmit Enable The MII Transmit
Enable signal indicates that valid data is
present on the MII_TXD[3:0] pins.
I
13
MII_CRS
MII Carrier Sense The MII Carrier Sense
signal is asserted within 30 MII clocks
after MII_TXEN indicates a TX frame is
being sent by the local host. MII CRS stays
true until the entire TX frame is loaded
into an internal buffer and a new buffer
is allocated to the MII TX interface. This
signal should be used monitored by the
MII TX host. A new MII TX frame should
not be sent until MII CRS returns to false
to prevent TX buffer overflows. MII_CRS is
an asynchronous output signal.
O
17
MII_TXER
MII Transmit Error Assertion of this signal
causes intentionally bad data to be
transmitted. The MII interface will discard
any incoming frame received when if this
signal is asserted while MII_TXEN is true.
I
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