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參數(shù)資料
| 型號： | 0002A01L |
| 英文描述： | FEMTOCLOCKS⑩ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER |
| 中文描述： | FEMTOCLOCKS⑩晶體到的LVCMOS / LVTTL頻率合成器 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 199K |
| 代理商： | 0002A01L |
Integrated
Circuit
Systems, Inc.
840002AG-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 13, 2006
8
ICS840002-01
FEMTOCLOCKSCRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
Figure 3 shows a schematic example of the ICS840002-01. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18
pF parallel resonant 25MHz crystal is used. The C1=22pF and
FIGURE 3. ICS840002-01 SCHEMATIC EXAMPLE
C2=22pF are recommended for frequency accuracy. For differ-
ent board layout, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. 1K
Ω pullup or pulldown resis-
tors can be used for the logic control input pins.
VDD
RD2
1K
X1
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
tied to ground.
C5
0.1u
XTAL2
XTAL1
VDDA
RU2
Not Install
C4
0.01u
To Logic
Input
pins
VDD
Set Logic
Input to
'1'
Zo = 50 Ohm
R3
100
Logic Control Input Examples
To Logic
Input
pins
Optional Termination
C6
0.1u
C2
22pF
Zo = 50 Ohm
R2
33
RU1
1K
RD1
Not Install
VDD
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
VDD
U1
ICS840002-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FSEL0
XTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
VDD
XTAL_OUT
XTAL_IN
VDDO
Q1
Q0
GND
FSEL1
C3
10uF
R4
100
Set Logic
Input to
'0'
R1
10
LVCMOS
C1
22pF
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
Ω
resistor can be tied from XTAL_IN to ground.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1k
Ω resistor can be tied from the TEST_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
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