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參數(shù)資料
| 型號(hào)： | μPD98401A |
| 廠商： | NEC Corp. |
| 英文描述： | ATM SAR Chip(高性能異步傳輸模式控制器) |
| 中文描述： | 自動(dòng)柜員機(jī)特區(qū)芯片（高性能異步傳輸模式控制器） |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大小： | 29K |
| 代理商： | ΜPD98401A |
Generic 32-bit multiplexed address/data bus interface
for simple connection to popular I/O buses (PCI, SBus,
GIO, APbus) with minimal glue logic
Up to 33-MHz operation with separate control signals
for bus master and slave operations
High-performance DMA controller with programmable
burst mode capability
Big Endian and little Endian formats
Four mail boxes that inform the host CPU of completed
frame transmission and reception and reduce CPU
interruptions
Scattering and gathering of data into and out of host
memory for more efficient CPU utilization
Flexible architecture with no restriction on transmit
buffer size or the number of entries that may be used
Up to 32 free buffer pools with flexible buffer sizes for
received traffic
UTOPIA interface for direct connection to the readily
available physical interface devices, such as NEC’s
μPD98404 SONET/SDH framer chip
Information transfers between the host CPU and NEC’s
μPD98404 SONET/SDH framer chip using its host
interface, eliminating the need for separate signaling
between the host and the framer chip
Loopback of transmit traffic to the receiving direction at
the UTOPIA (PHY) interface side
Access pins for self-testing
J TAG boundary scan option for automatic testing
Low-power CMOS technology (0.8-micron)
208-pin PQFP package
ATM adapter cards
Internetworking devices (bridges and routers)
Workstations and servers
H O S T I N T E R F A C E
G E N E R A L
A P P L I C A T I O N S
M E D I A I N T E R F A C E
T R A F F I C M A N A G E M E N T
A N D C O N T R O L
levels. The μPD98401A incorporates 16 shapers using the
dual leaky bucket algorithm for traffic management. The host
specifies an associated shaper for each active channel. Each
shaper has a priority level, an average traffic rate, and a
peak rate. These parameters are supplied to a set of internal
shaper registers by the host and may be modified at any
time to allow for flexible traffic flow control.
The transmit queues consist of multiple packet descriptors
associated with various active connections. A single packet
may reside in one or more buffers. The read pointer of the
transmit queue resides in a transmit VC table located in con-
trol memory. Its initialization is done by the host and then
modified by the μPD98401A each time it fetches a new data
segment for transmission.
A packet descriptor may contain either a pointer to a data
buffer or, in the case of multiple buffers per packet, a pointer
to a packet directory. The μPD98401A stores the read
address and the remaining size of the active buffer for each
connection in the transmit VC table. This mechanism limits
access to the transmit queue and/or packet directory to
when a new data buffer is needed.
Received traffic is stored in buffers in system memory. The
host supplies 32 pools of free buffer descriptors. Each pool
consists of link-list batches of free buffer descriptors. Each
batch consists of one or more buffer descriptors and ends
with a batch link pointer. An entry in the VC table instructs
each VC of its assigned pool. The buffer sizes are flexible
and may range from 64 bytes to 64K bytes.
After the scheduler selects the channel to be served, the
transmit operation begins by fetching a segment of the
packet from system memory. The μPD98401A transmit cir-
cuitry constructs an ATM cell by tagging header information,
excluding the HEC, to the fetched data segment. The header
information is based on data retrieved from the VC table.
The cell is then staged in the integrated transmit FIFO until
ready to be transferred to the physical interface device.
The transmit circuitry is responsible for maintaining relevant
information on the currently active transmit buffer in the VC
table. When a buffer is exhausted, the transmit circuit
fetches a new number from system memory and places all
necessary information in the VC table. The transmit circuitry
deactivates a channel when its transmit queue is exhausted.
The μPD98401 supports a maximum of 32,000 active virtual
channels (VCs). Scheduling of data flow from the various
active channels is done by an on-chip scheduler according
to the channel’s traffic shaping parameters and prority
T R A N S M I T Q U E U E S
R E C E I V E D Q U E U E S
T R A N S M I T O P E R A T I O N
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