
19
5.3.3
5.3.4
Operand Address Addressing .........................................................................................
5.4.1
Implied addressing ..............................................................................................................
5.4.2
Register addressing.............................................................................................................
5.4.3
Direct addressing.................................................................................................................
5.4.4
Short direct addressing........................................................................................................
5.4.5
Special-Function Register (SFR) addressing ......................................................................
5.4.6
Register indirect addressing ................................................................................................
5.4.7
Based addressing ................................................................................................................
5.4.8
Based indexed addressing ..................................................................................................
5.4.9
Stack addressing .................................................................................................................
Table indirect addressing .....................................................................................................
Register addressing.............................................................................................................
120
120
121
121
122
123
124
125
126
127
128
128
5.4
CHAPTER 6
6.1
6.2
PORT FUNCTIONS ....................................................................................................
Port Functions...................................................................................................................
Port Configuration ............................................................................................................
6.2.1
Port 0 ...................................................................................................................................
6.2.2
Port 1 ...................................................................................................................................
6.2.3
Port 2 (
μ
PD78054 Subseries)..............................................................................................
6.2.4
Port 2 (
μ
PD78054Y Subseries) ...........................................................................................
6.2.5
Port 3 ...................................................................................................................................
6.2.6
Port 4 ...................................................................................................................................
6.2.7
Port 5 ...................................................................................................................................
6.2.8
Port 6 ...................................................................................................................................
6.2.9
Port 7 ...................................................................................................................................
6.2.10
Port 12 .................................................................................................................................
6.2.11
Port 13 .................................................................................................................................
Port Function Control Registers .....................................................................................
Port Function Operations.................................................................................................
6.4.1
Writing to input/output port...................................................................................................
6.4.2
Reading from input/output port ............................................................................................
6.4.3
Operations on input/output port ...........................................................................................
Selection of Mask Option .................................................................................................
129
129
134
134
136
137
139
141
142
143
144
146
148
149
150
156
156
156
157
157
6.3
6.4
6.5
CHAPTER 7
7.1
7.2
7.3
7.4
CLOCK GENERATOR ................................................................................................
Clock Generator Functions..............................................................................................
Clock Generator Configuration .......................................................................................
Clock Generator Control Register...................................................................................
System Clock Oscillator...................................................................................................
7.4.1
Main system clock oscillator ................................................................................................
7.4.2
Subsystem clock oscillator ..................................................................................................
7.4.3
Scaler...................................................................................................................................
7.4.4
When no subsystem clocks are used ..................................................................................
Clock Generator Operations ............................................................................................
7.5.1
Main system clock operations .............................................................................................
7.5.2
Subsystem clock operations ................................................................................................
Changing System Clock and CPU Clock Settings.........................................................
7.6.1
Time required for switchover between system clock and CPU clock ..................................
7.6.2
System clock and CPU clock switching procedure..............................................................
159
159
159
161
165
165
166
168
168
169
170
171
171
171
173
7.5
7.6