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參數(shù)資料
| 型號： | μPD78F9418 |
| 廠商： | NEC Corp. |
| 英文描述： | 8 Bit Single Chip Microcontrollers(8位單片微控制器) |
| 中文描述： | 8位單片機微控制器（8位單片微控制器） |
| 文件頁數(shù)： | 65/128頁 |
| 文件大?。?/td> | 614K |
| 代理商： | ΜPD78F9418 |
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65
μ
PD78F9418
(1) Transmission shift register (TXS)
The TXS is a register in which transmission data is prepared. The transmission data is output from the TXS
bit-serially.
When the data length is seven bits, bits 0 to 6 of the data in the TXS will be transmission data. Writing data to
the TXS triggers transmission.
The TXS can be write-accessed, using an 8-bit memory manipulation instruction, but cannot be read-accessed.
A RESET input loads FFH into the TXS.
Caution
Do not write to the TXS during transmission.
The TXS and the reception buffer register (RXB) are mapped at the same address, such that
any attempt to read from the TXS results in a value being read from the RXB.
(2) Reception shift register (RXS)
The RXS is a register in which serial data, received at the RxD pin, is converted to parallel data. Once one entire
byte has been received, the RXS feeds the reception data to the reception buffer register (RXB).
The RXS cannot be manipulated directly by a program.
(3) Reception buffer register (RXB)
The RXB is used to hold reception data. Once the RXS has received one entire byte of data, it feeds that data
into the RXB.
When the data length is seven bits, the reception data is sent to bits 0 to 6 of the RXB, in which the MSB is fixed
to 0.
The RXB can be read-accessed, using an 8-bit memory manipulation instruction, but cannot be write-accessed.
A RESET input makes the RXB undefined.
Caution
The RXB and the transmission shift register (TXS) are mapped at the same address, such that
any attempt to write to the RXB results in a value being written to the TXS.
(4) Transmission control circuit
The transmission control circuit controls transmission. For example, it adds start, parity, and stop bits to the data
in the transmission shift register (TXS), according to the setting of the asynchronous serial interface mode
register (ASIM).
(5) Reception control circuit
The reception control circuit controls reception according to the setting of the asynchronous serial interface mode
register (ASIM). It also checks for errors, such as parity errors, during reception. If an error is detected, the
asynchronous serial interface status register (ASIS) is set according to the status of the error.
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