參數(shù)資料
型號(hào)： μPD78F9197Y
廠商： NEC Corp.
英文描述： 8 Bit Single Chip Microcontrollers(8 位單片微控制器)
中文描述： 8位單片機(jī)微控制器（8位單片微控制器）
文件頁數(shù)： 122/150頁
文件大?。?/td> 636K
代理商： ΜPD78F9197Y
Preliminary Product Information
122
μ
PD78F9197Y
Mnemonic
Operand
Byte
Clock
Operation
Flag
Z
AC CY
XCHW
AX, rp
Note
1
8
AX
rp
ADD
A, #byte
2
4
A, CY
←
A + byte
×
×
×
saddr, #byte
3
6
(saddr), CY
←
(saddr) + byte
×
×
×
A, r
2
4
A, CY
←
A + r
×
×
×
A, saddr
2
4
A, CY
←
A + (saddr)
×
×
×
A, !addr16
3
8
A, CY
←
A + (addr16)
×
×
×
A, [HL]
1
6
A, CY
←
A + (HL)
×
×
×
A, [HL + byte]
2
6
A, CY
←
A + (HL + byte)
×
×
×
ADDC
A, #byte
2
4
A, CY
←
A + byte + CY
×
×
×
saddr, #byte
3
6
(saddr), CY
←
(saddr) + byte + CY
×
×
×
A, r
2
4
A, CY
←
A + r + CY
×
×
×
A, saddr
2
4
A, CY
←
A + (saddr) + CY
×
×
×
A, !addr16
3
8
A, CY
←
A + (addr16) + CY
×
×
×
A, [HL]
1
6
A, CY
←
A + (HL) + CY
×
×
×
A, [HL + byte]
2
6
A, CY
←
A + (HL + byte) + CY
×
×
×
SUB
A, #byte
2
4
A, CY
←
A
byte
×
×
×
saddr, #byte
3
6
(saddr), CY
←
(saddr)
byte
×
×
×
A, r
2
4
A, CY
←
A
r
×
×
×
A, saddr
2
4
A, CY
←
A
(saddr)
×
×
×
A, !addr16
3
8
A, CY
←
A
(addr16)
×
×
×
A, [HL]
1
6
A, CY
←
A
(HL)
×
×
×
A, [HL + byte]
2
6
A, CY
←
A
(HL + byte)
×
×
×
SUBC
A, #byte
2
4
A, CY
←
A
byte
CY
×
×
×
saddr, #byte
3
6
(saddr), CY
←
(saddr)
byte
CY
×
×
×
A, r
2
4
A, CY
←
A
r
CY
×
×
×
A, saddr
2
4
A, CY
←
A
(saddr)
CY
×
×
×
A, !addr16
3
8
A, CY
←
A
(addr16)
CY
×
×
×
A, [HL]
1
6
A, CY
←
A
(HL)
CY
×
×
×
A, [HL + byte]
2
6
A, CY
←
A
(HL + byte)
CY
×
×
×
AND
A, #byte
2
4
A
←
A
∧
byte
×
saddr, #byte
3
6
(saddr)
←
(saddr)
∧
byte
×
A, r
2
4
A
←
A
∧
r
×
A, saddr
2
4
A
←
A
∧
(saddr)
×
A, !addr16
3
8
A
←
A
∧
(addr16)
×
A, [HL]
1
6
A
←
A
∧
(HL)
×
A, [HL + byte]
2
6
A
←
A
∧
(HL + byte)
×
Note
Only when rp = BC, DE, or HL.
Remark
The instruction clock cycle is based on the CPU clock (f
CPU
), specified in the processor clock controller
register (PCC).
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