參數(shù)資料
型號: μPD78F9136
廠商: NEC Corp.
英文描述: 8 Bit Single Chip Microcontrollers(8 位單片微控制器)
中文描述: 8位單片機(jī)微控制器(8位單片微控制器)
文件頁數(shù): 27/44頁
文件大小: 212K
代理商: ΜPD78F9136
Preliminary Product Information
27
PD78F9136
(2) Serial interface (T
A
= -40 to +85 C, V
DD
= 1.8 to 5.5 V)
(i) Three-wire serial I/O mode (SCK20...Internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK20 cycle time
t
KCY1
V
DD
= 2.7 to 5.5 V
1 000
ns
4 000
ns
V
DD
= 2.7 to 5.5 V
t
KCY1
/2-50
ns
t
KCY1
/2-150
ns
t
SIK1
V
DD
= 2.7 to 5.5 V
150
ns
500
ns
t
KSI1
V
DD
= 2.7 to 5.5 V
400
ns
600
ns
t
KSO1
V
DD
= 2.7 to 5.5 V
0
250
ns
0
1 000
ns
Note
R and C are the resistance and capacitance of the SO20 output line, respectively.
(ii) Three-wire serial I/O mode (SCK20...External clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK20 cycle time
t
KCY2
V
DD
= 2.7 to 5.5 V
1 000
ns
4 000
ns
V
DD
= 2.7 to 5.5 V
400
ns
1 600
ns
t
SIK2
V
DD
= 2.7 to 5.5 V
100
ns
150
ns
t
KSI2
V
DD
= 2.7 to 5.5 V
400
ns
600
ns
t
KSO2
V
DD
= 2.7 to 5.5 V
0
300
ns
0
1 000
ns
t
KAS2
V
DD
= 2.7 to 5.5 V
120
ns
400
ns
t
KDS2
V
DD
= 2.7 to 5.5 V
240
ns
800
ns
Note
R and C are the resistance and capacitance of the SO20 output line, respectively.
(iii) UART mode (internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Transfer rate
V
DD
= 2.7 to 5.5 V
78 125
bps
19 531
bps
SCK20 high/low
level width
SI20 setup time
(for SCK20 latch edge)
SI20 hold time
(for SCK20 latch edge)
Delay from SCK20 shift
edge to SO20 output
SCK20 high/low
level width
SI20 setup time
(for SCK20 latch edge)
SI20 hold time
(for SCK20 latch edge)
Delay from SCK20 shift
edge to SO20 output
t
KH2
,
t
KL2
t
KH1
,
t
KL1
R = 1 k ,
C = 100 pF
Note
R = 1 k ,
C = 100 pF
Note
SO20 setup time
(for SS20 when
SS20 is used)
SO20 disable time
(for SS20 when
SS20 is used)
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