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CHAPTER 9 8-BIT TIMER/EVENT COUNTER
Table 9-9. Interval Times When 2-channel 8-bit Timer/Event Counters (TM1 and TM2)
Are Used as 16-bit Timer/Event Counter
TCL13 TCL12 TCL11 TCL10
Minimum Interval Time
Maximum Interval Time
Resolution
MCS = 1
MCS = 0
MCS = 1
MCS = 0
MCS = 1
MCS = 0
0
0
0
0
TI1 input cycle
2
8
×
TI1 input cycle
TI1 input edge cycle
0
0
0
1
TI1 input cycle
2
8
×
TI1 input cycle
TI1 input edge cycle
0
1
1
0
2
×
1/f
X
(400 ns)
2
2
×
1/f
X
(800 ns)
2
17
×
1/f
X
(26.2 ms)
2
18
×
1/f
X
(52.4 ms)
2
×
1/f
X
(400 ns)
2
2
×
1/f
X
(800 ns)
0
1
1
1
2
2
×
1/f
X
(800 ns)
2
3
×
1/f
X
(1.6
μ
s)
2
18
×
1/f
X
(52.4 ms)
2
19
×
1/f
X
(104.9 ms)
2
2
×
1/f
X
(800 ns)
2
3
×
1/f
X
(1.6
μ
s)
1
0
0
0
2
3
×
1/f
X
(1.6
μ
s)
2
4
×
1/f
X
(3.2
μ
s)
2
19
×
1/f
X
(104.9 ms)
2
20
×
1/f
X
(209.7 ms)
2
3
×
1/f
X
(1.6
μ
s)
2
4
×
1/f
X
(3.2
μ
s)
1
0
0
1
2
4
×
1/f
X
(3.2
μ
s)
2
5
×
1/f
X
(6.4
μ
s)
2
20
×
1/f
X
(209.7 ms)
2
21
×
1/f
X
(419.4 ms)
2
4
×
1/f
X
(3.2
μ
s)
2
5
×
1/f
X
(6.4
μ
s)
1
0
1
0
2
5
×
1/f
X
(6.4
μ
s)
2
6
×
1/f
X
(12.8
μ
s)
2
21
×
1/f
X
(419.4 ms)
2
22
×
1/f
X
(838.9 ms)
2
5
×
1/f
X
(6.4
μ
s)
2
6
×
1/f
X
(12.8
μ
s)
1
0
1
1
2
6
×
1/f
X
(12.8
μ
s)
2
7
×
1/f
X
(25.6
μ
s)
2
22
×
1/f
X
(838.9 ms)
2
23
×
1/f
X
(1.7 s)
2
6
×
1/f
X
(12.8
μ
s)
2
7
×
1/f
X
(25.6
μ
s)
1
1
0
0
2
7
×
1/f
X
(25.6
μ
s)
2
8
×
1/f
X
(51.2
μ
s)
2
23
×
1/f
X
(1.7 s)
2
24
×
1/f
X
(3.4 s)
2
7
×
1/f
X
(25.6
μ
s)
2
8
×
1/f
X
(51.2
μ
s)
1
1
0
1
2
8
×
1/f
X
(51.2
μ
s)
2
9
×
1/f
X
(102.4
μ
s)
2
24
×
1/f
X
(3.4 s)
2
25
×
1/f
X
(6.7 s)
2
8
×
1/f
X
(51.2
μ
s)
2
9
×
1/f
X
(102.4
μ
s)
1
1
1
0
2
9
×
1/f
X
(102.4
μ
s)
2
10
×
1/f
X
(204.8
μ
s)
2
25
×
1/f
X
(6.7 s)
2
26
×
1/f
X
(13.4 s)
2
9
×
1/f
X
(102.4
μ
s)
2
10
×
1/f
X
(204.8
μ
s)
1
1
1
1
2
11
×
1/f
X
(409.6
μ
s)
2
12
×
1/f
X
(819.2
μ
s)
2
27
×
1/f
X
(26.8 s)
2
28
×
1/f
X
(53.7 s)
2
11
×
1/f
X
(409.6
μ
s)
2
12
×
1/f
X
(819.2
μ
s)
Other than above
Setting prohibited
Remarks 1.
f
X
: Main system clock oscillation frequency
: Bit 0 of oscillation mode selection register (OSMS)
3.
TCL10 to TCL13 : Bits 0 to 3 of timer clock select register 1 (TCL1)
4.
Values in parentheses apply to operation with f
X
= 5.0 MHz.
2.
MCS