
43
CHAPTER 2 OUTLINE (
μ
PD780058Y Subseries)
2.4 Pin Configuration (Top View)
80-pin plastic QFP (14
×
14 mm, Resin thickness: 2.7 mm)
Note
μ
PD780053YGC-
×××
-3B9, 780054YGC-
×××
-3B9, 780055YGC-
×××
-3B9,
μ
PD780056YGC-
×××
-3B9, 780058YGC-
×××
-3B9, 78F0058YGC-3B9
80-pin plastic QFP (14
×
14 mm, Resin thickness: 1.4 mm)
Note
μ
PD780053YGC-
×××
-8BT, 780054YGC-
×××
-8BT, 780055YGC-
×××
-8BT,
μ
PD780056YGC-
×××
-8BT, 780058YGC-
×××
-8BT, 78F0058YGC-8BT
80-pin plastic TQFP (Fine pitch) (12
×
12 mm)
Note
μ
PD780053YGK-
×××
-BE9, 780054YGK-
×××
-BE9, 780055YGK-
×××
-BE9,
μ
PD780056YGK-
×××
-BE9, 780058YGK-
×××
-BE9, 78F0058YGK-BE9
Note
Under planning
Cautions 1. Be sure to connect IC (Internally Connected) pin to V
SS0
directly in normal operating
mode.
2. Connect AV
SS
pin to V
SS0
.
Remarks 1.
Pin connection in parentheses is intended for the
μ
PD78F0058Y.
2.
When the
μ
PD780053Y, 780054Y, 780055Y, 780056Y, or 780058Y is used in application fields
that require reduction of the noise generated from inside the microcontroller, the implementation
of noise reduction measures, such as supplying to V
DD0
and V
DD1
individually and connecting
V
SS0
and V
SS1
to different ground lines, is recommended.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P15/ANI5
P16/ANI6
P17/ANI7
AV
SS
P130/ANO0
P131/ANO1
AV
REF1
P70/SI2/RxD0
P71/SO2/TxD0
P72/SCK2/ASCK
P20/SI1
P21/SO1
P22/SCK1
P23/STB/TxD1
P24/BUSY/RxD1
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P40/AD0
P41/AD1
RESET
P127/RTP7
P126/RTP6
P125/RTP5
P124/RTP4
P123/RTP3
P122/RTP2
P121/RTP1
P120/RTP0
P37
P36/BUZ
P35/PCL
P34/TI2
P33/TI1
P32/TO2
P31/TO1
P30/TO0
P67/ASTB
P66/WAIT
P65/WR
P
P
P
P
P
A
R
V
D
X
X
I
P
)
X
X
V
D
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
V
S
P
P
P
P
P
P
P
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
V
S