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LIST OF FIGURES (2/5)
Figure No.
Title
Page
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
16-Bit Timer/Event Counter Block Diagram ......................................................................................
16-Bit Timer Mode Control Register (TMC0) Format ........................................................................
Capture/Compare Control Register 0 (CRC0) Format......................................................................
16-Bit Timer Output Control Register L (TOC0) Format....................................................................
Prescaler Mode Register 0 (PRM0) Format .....................................................................................
Port Mode Register 7 (PM7) Format.................................................................................................
Control Register Settings for Interval Timer Operation .....................................................................
Interval Timer Configuration Diagram ...............................................................................................
Timing of Interval Timer Operation....................................................................................................
Control Register Settings for PPG Output Operation .......................................................................
Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register ................................................................................................................
Configuration Diagram for Pulse Width Measurement by Free-Running Counter ............................
Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture
Register (with Both Edges Specified) ...............................................................................................
Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter ........
Capture Operation with Rising Edge Specified.................................................................................
Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified)..............................................................................................................
Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers .....................................................................................................................
Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture
Registers (with Rising Edge Specified).............................................................................................
Control Register Settings for Pulse Width Measurement by Means of Restart ................................
Timing of Pulse Width Measurement Operation by Means of Restart
(with Rising Edge Specified) .............................................................................................................
Control Register Settings in External Event Counter Mode ..............................................................
External Event Counter Configuration Diagram................................................................................
External Event Counter Operation Timings (with Rising Edge Specified) ........................................
Control Register Settings in Square-Wave Output Mode .................................................................
Square-Wave Output Operation Timing ............................................................................................
Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger ................
Timing of One-Shot Pulse Output Operation Using Software Trigger...............................................
16-Bit Timer Register Start Timing ....................................................................................................
Timings After Change of Compare Register During Timer Count Operation ....................................
Capture Register Data Retention Timing ..........................................................................................
Operation Timing of OVF0 Flag ........................................................................................................
159
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164
165
166
167
168
169
169
170
171
172
8-12
8-13
172
173
174
8-14
8-15
8-16
174
8-17
175
8-18
176
177
8-19
8-20
177
178
179
179
180
181
182
183
184
184
185
186
8-21
8-22
8-23
8-24
8-25
8-26
8-27
8-28
8-29
8-30
8-31
9-1
9-2
9-3
9-4
9-5
9-6
9-7
8-Bit Timer/Event Counter 50 Block Diagram ...................................................................................
8-Bit Timer/Event Counter 51 Block Diagram ...................................................................................
Timer Clock Select Register 50 (TCL50) Format ..............................................................................
Timer Clock Select Register 51 (TCL51) Format ..............................................................................
8-Bit Timer Mode Control Register 5n (TMC5n) Format ...................................................................
Port Mode Register 7 (PM7) Format.................................................................................................
Interval Timer Operation Timings ......................................................................................................
190
190
192
193
194
195
197