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| 型號(hào)： | μPD789014 |
| 廠商： | NEC Corp. |
| 英文描述： | 8 Bit Single Chip Microcontrollers(8位單片微控制器) |
| 中文描述： | 8位單片機(jī)微控制器（8位單片微控制器） |
| 文件頁(yè)數(shù)： | 25/125頁(yè) |
| 文件大小： | 366K |
| 代理商： | ΜPD789014 |
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CHAPTER 2 REGISTERS
8
(1)
Interrupt enable flag (IE)
This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, the CPU is placed in the disable interrupt (DI) state, in which all interrupts other than
nonmaskable interrupts are disabled.
When IE = 1, the CPU is placed in the enable interrupt (EI) state, in which the acknowledgment of interrupt
requests is controlled by the interrupt mask flag for each interrupt source.
The IE flag is reset to (0) upon DI instruction execution or interrupt acknowledgment and is set to (1) upon
EI instruction execution.
(2)
Zero flag (Z)
When the operation result is zero, this flag is set to (1). It is reset to (0) in all other cases.
(3)
Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to (1). It is reset to (0) in all
other cases.
(4)
Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction
execution.
2.1.3 Stack Pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area.
Figure 2-3. Stack Pointer Configuration
15
0
SP
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the
stack memory.
Each stack operation saves/resets data as shown in Figures 2-4 and 2-5.
Caution
Since
execution.
______
RESET input makes SP contents undefined, be sure to initialize the SP before instruction
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