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CHAPTER 13 A/D CONVERTER
Figure 13-17. Example of Capacitor Connection on A/D Converter Pins
(3) When the STOP mode or IDLE mode is used, the consumption current should be reduced by clearing (0) the AM0
bit and AM1 bit before entering the STOP or IDLE mode. If the AM0 bit and AM1 bit remains set (1), the conversion
operation will be stopped by entering the STOP or IDLE mode, but the power supply to the voltage comparator will
not be stopped, and therefore the A/D converter consumption current will not be reduced.
(4) Once the A/D converter starts operating, conversion operations are performed repeatedly until the AM0 bit and AM1
bit of the A/D converter mode (ADM) is cleared (0). Therefore, a superfluous interrupt may be generated if ADM
setting is performed after interrupt-related registers, etc., are set when A/D converter mode conversion, etc., is
performed. The result of this superfluous interrupt is that the conversion result storage address appears to have
been shifted when the scan mode is used. Also, when the select mode is used, the first conversion result appears
to have been an abnormal value, such as the conversion result for the other channel. It is therefore recommended
that A/D converter mode conversion be carried out using the following procedure.
<1>
<2>
<3>
Write to the ADM
Interrupt request flag (ADIF) clearance (0)
Interrupt mask flag setting
Operations <1> to <3> should not be divided by an interrupt or macro service.
Alternatively, the following procedure is recommended.
<1>
<2>
<3>
<4>
Stop the A/D conversion operation by clearing (0) the AM0 bit and AM1 bit of the ADM.
Interrupt request flag (ADIF) clearance (0).
Interrupt mask flag setting
Write to the ADM
Analog
Input
Reference
Voltage Input
100 to
500 pF
ANI0-ANI15
AV
REF
AV
SS
μ
PD784046