
47
CHAPTER 4 INSTRUCTION SET
8-Bit
ADDC
A,#byte
2
8
–
A,CY
←
A+byte+CY
×
×
×
Operation
saddr,#byte
3
12
16
(saddr), CY
←
(saddr)+byte+CY
×
×
×
A,r
Note 3
2
8
–
A,CY
←
A+r+CY
×
×
×
r,A
2
8
–
r,CY
←
r+A+CY
×
×
×
A,saddr
2
8
10
A,CY
←
A+(saddr)+CY
×
×
×
A,!addr16
3
16
18+2n
A,CY
←
A+(addr16)+CY
×
×
×
A,[HL]
1
8
10+2n
A,CY
←
A+(HL)+CY
×
×
×
A,[HL+byte]
2
16
18+2n
A,CY
←
A+(HL+byte)+CY
×
×
×
A,[HL+B]
2
16
18+2n
A,CY
←
A+(HL+B)+CY
×
×
×
A,[HL+C]
2
16
18+2n
A,CY
←
A+(HL+C)+CY
×
×
×
SUB
A,#byte
2
8
–
A,CY
←
A–byte
×
×
×
saddr,#byte
3
12
16
(saddr),CY
←
(saddr)– byte
×
×
×
A,r
Note 3
2
8
–
A,CY
←
A–r
×
×
×
r,A
2
8
–
r,CY
←
r–A
×
×
×
A,saddr
2
8
10
A,CY
←
A–(saddr)
×
×
×
A,!addr16
3
16
18+2n
A,CY
←
A–(addr16)
×
×
×
A,[HL]
1
8
10+2n
A,CY
←
A–(HL)
×
×
×
A,[HL+byte]
2
16
18+2n
A,CY
←
A–(HL+byte)
×
×
×
A,[HL+B]
2
16
18+2n
A,CY
←
A–(HL+B)
×
×
×
A,[HL+C]
2
16
18+2n
A,CY
←
A–(HL+C)
×
×
×
SUBC
A,#byte
2
8
–
A,CY
←
A–byte–CY
×
×
×
saddr,#byte
3
12
16
(saddr),CY
←
(saddr)–byte–CY
×
×
×
A,r
Note 3
2
8
–
A,CY
←
A–r–CY
×
×
×
r,A
2
8
–
r,CY
←
r–A–CY
×
×
×
A,saddr
2
8
10
A,CY
←
A–(saddr)–CY
×
×
×
A,!addr16
3
16
18+2n
A,CY
←
A–(addr16)–CY
×
×
×
A,[HL]
1
8
10+2n
A,CY
←
A–(HL)–CY
×
×
×
A,[HL+byte]
2
16
18+2n
A,CY
←
A–(HL+byte)–CY
×
×
×
A,[HL+B]
2
16
18+2n
A,CY
←
A–(HL+B)–CY
×
×
×
A,[HL+C]
2
16
18+2n
A,CY
←
A–(HL+C)–CY
×
×
×
Notes 1.
When the internal high-speed RAM area is accessed or in the instruction with no data access.
When an area except the internal high-speed RAM area is accessed.
Except r = A.
2.
3.
Remarks 1.
1 instruction clock cycle is 1 CPU clock cycle (f
CPU
) selected by the processor clock control register
(PCC).
Number of clock cycles is when there is a program in the internal ROM area.
n indicates the number of waits when the external memory expansion area is read.
2.
3.
Instruction
Group
Clock
Flag
Mnemonic
Operands
Byte
Operation
Note 1
Note 2
Z AC CY