49
CHAPTER 4 INSTRUCTION SET
8-Bit
CMP
A,#byte
2
8
–
A–byte
×
×
×
Operation
saddr,#byte
3
12
16
(saddr)–byte
×
×
×
A,r
Note 3
2
8
–
A–r
×
×
×
r,A
2
8
–
r–A
×
×
×
A,saddr
2
8
10
A–(saddr)
×
×
×
A,!addr16
3
16
18+2n
A–(addr16)
×
×
×
A,[HL]
1
8
10+2n
A–(HL)
×
×
×
A,[HL+byte]
2
16
18+2n
A–(HL+byte)
×
×
×
A,[HL+B]
2
16
18+2n
A–(HL+B)
×
×
×
A,[HL+C]
2
16
18+2n
A–(HL+C)
×
×
×
16-Bit
ADDW
AX,#word
3
12
–
AX,CY
←
AX+word
×
×
×
Operation
SUBW
AX,#word
3
12
–
AX,CY
←
AX–word
×
×
×
CMPW
AX,#word
3
12
–
AX–word
×
×
×
Multiply/
MULU
Note 4
X
2
32
–
AX
←
A
×
X
divide
DIVUW
Note 4
C
2
50
–
AX (quotient), C (remainder)
←
AX
÷
C
Increment/
INC
r
1
4
–
r
←
r+1
×
×
decrement
saddr
2
8
12
(saddr)
←
(saddr)+1
×
×
DEC
r
1
4
–
r
←
r–1
×
×
saddr
2
8
12
(saddr)
←
(saddr)–1
×
×
INCW
rp
1
8
–
rp
←
rp+1
DECW
rp
1
8
–
rp
←
rp–1
Rotate
ROR
A,1
1
4
–
(CY, A
7
←
A
0
, A
m–1
←
A
m
)
×
1
×
ROL
A,1
1
4
–
(CY, A
0
←
A
7
, A
m+1
←
A
m
)
×
1
×
RORC
A,1
1
4
–
(CY
←
A
0
, A
7
←
CY, A
m–1
←
A
m
)
×
1
×
ROLC
A,1
1
4
–
(CY
←
A
7
, A
0
←
CY, A
m+1
←
A
m
)
×
1
×
ROR4
[HL]
2
20
24+2n+2m
A
3–0
←
(HL)
3–0
, (HL)
7–4
←
A
3–0
, (HL)
3–0
←
(HL)
7–4
ROL4
[HL]
2
20
24+2n+2m
A
3–0
←
(HL)
7–4
, (HL)
3–0
←
A
3–0
, (HL)
7–4
←
(HL)
3–0
BCD Adjust
ADJBA
2
8
–
Decimal Adjust Accumulator after Addition
×
×
×
ADJBS
2
8
–
Decimal Adjust Accumulator after Subtract
×
×
×
Notes 1.
When the internal high-speed RAM area is accessed or in the instruction with no data access.
When an area except the internal high-speed RAM area is accessed.
Except r = A.
The
μ
PD78002/78002Y Subseries have no MULU/DIVUW instructions.
2.
3.
4.
Remarks 1.
1 instruction clock cycle is 1 CPU clock cycle (f
CPU
) selected by the processor clock control register
(PCC).
Number of clock cycles is when there is a program in the internal ROM area.
n indicates the number of waits when the external memory expansion area is read.
m indicates the number of waits when the external memory expansion area is written to.
2.
3.
4.
Instruction
Group
Clock
Flag
Mnemonic
Operands
Byte
Operation
Note 1
Note 2
Z AC CY