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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER
Figure 5-2. Format of Timer Clock Select Register 0 (
μ
PD78098, 78098B subseries)
TCL03 TCL02 TCL01 TCL00
Selects clock of PCL output
0
0
0
0
f
XT
(32.768 kHz)
0
1
0
1
f
XX
(4.0 MHz)
0
1
1
0
f
XX
/2 (2.0 MHz)
0
1
1
1
f
XX
/2
2
(1.0 MHz)
1
0
0
0
f
XX
/2
3
(500 kHz)
1
0
0
1
f
XX
/2
4
(250 kHz)
1
0
1
0
f
XX
/2
5
(125 kHz)
1
0
1
1
f
XX
/2
6
(62.5 kHz)
1
1
0
0
f
XX
/2
7
(31.3 kHz)
Others
Setting prohibited
TCL06 TCL05 TCL04
Selects count clock of 16-bit timer register
0
0
0
TI00 (valid edge can be specified)
0
0
1
2f
XX
Note
0
1
0
f
XX
(4.0 MHz)
0
1
1
f
XX
/2 (2.0 MHz)
1
0
0
f
XX
/2
2
(1.0 MHz)
1
1
1
Watch timer output (INTTM3)
Others
Setting prohibited
CLOE
Controls PCL output
0
Disables output
1
Enables output
Note
At f
XX
> 2.5 MHz, setting prohibited.
Cautions 1. The valid edge of the TI00/INTP0 pin is specified by the external interrupt mode register 0
(INTM0). The frequency of the sampling clock is selected by the sampling clock select register
(SCS).
2. To enable PCL output, set TCL00 through TCL03, and then set CLOE to 1 by using a 1-bit
memory manipulation instruction.
3. Read the count value from TM0, not from the capture/compare register 01(CR01), when TI00
is specified as the count clock of TM0.
4. Before writing new data to TCL0, stop the timer operation once.
Remarks 1.
f
XX
: main system clock frequency
: subsystem clock oscillation frequency
3.
TI00: input pin of 16-bit timer/event counter
4.
TM0 : 16-bit timer register
5.
( ) : at f
XX
= 4.0 MHz or f
XT
= 32.768 kHz
2.
f
XT
7
6
5
4
3
2
Symbol
1
0
FF40H
TCL00
TCL0
TCL01
TCL03 TCL02
TCL04
TCL05
TCL06
CLOE
Address
At reset
R/W
00H
R/W