
51
CHAPTER 4 INSTRUCTION SET
Bit
CLR1
saddr.bit
2
8
12
(saddr.bit)
←
0
Manipulation
sfr.bit
3
–
16
sfr.bit
←
0
A.bit
2
8
–
A.bit
←
0
PSW.bit
2
–
12
PSW.bit
←
0
×
×
×
[HL].bit
2
12
16+2n+2m
(HL).bit
←
0
SET1
CY
1
4
–
CY
←
1
1
CLR1
CY
1
4
–
CY
←
0
0
NOT1
CY
1
4
–
CY
←
CY
×
Call Return
CALL
!addr16
3
14
–
(SP–1)
←
(PC+3)
H
, (SP–2)
←
(PC+3)
L
,
PC
←
addr16, SP
←
SP–2
CALLF
!addr11
2
10
–
(SP–1)
←
(PC+2)
H
, (SP–2)
←
(PC+2)
L
,
PC
15–11
←
00001, PC
10–0
←
addr11,
SP
←
SP–2
CALLT
[addr5]
1
12
–
(SP–1)
←
(PC+1)
H
, (SP–2)
←
(PC+1)
L
,
PC
H
←
(00000000, addr5+1),
PC
L
←
(00000000, addr5), SP
←
SP–2
BRK
1
12
–
(SP–1)
←
PSW, (SP–2)
←
(PC+1)
H
,
(SP–3)
←
(PC+1)
L
, PC
H
←
(003FH),
PC
L
←
(003EH), SP
←
SP–3, IE
←
0
RET
1
12
–
PC
H
←
(SP+1), PC
L
←
(SP), SP
←
SP+2
RETI
1
12
–
PC
H
←
(SP+1), PC
L
←
(SP),
PSW
←
(SP+2), SP
←
SP+3, NMIS
←
0
R R R
RETB
1
12
–
PC
H
←
(SP+1), PC
L
←
(SP),
PSW
←
(SP+2), SP
←
SP+3
R R R
Stack
PUSH
PSW
1
4
–
(SP–1)
←
PSW, SP
←
SP–1
Manipulation
rp
1
8
–
(SP–1)
←
rp
H
, (SP–2)
←
rp
L
, SP
←
SP–2
POP
PSW
1
4
–
PSW
←
(SP), SP
←
SP+1
R R R
rp
1
8
–
rp
H
←
(SP+1), rp
L
←
(SP), SP
←
SP+2
MOVW
SP,#word
4
–
20
SP
←
word
SP, AX
2
–
16
SP
←
AX
AX, SP
2
–
16
AX
←
SP
Unconditional
BR
!addr16
3
12
–
PC
←
addr16
Branch
$addr16
2
12
–
PC
←
PC+2+jdisp8
AX
2
16
–
PC
H
←
A, PC
L
←
X
Notes 1.
When the internal high-speed RAM area is accessed or in the instruction with no data access.
When an area except the internal high-speed RAM area is accessed.
2.
Remarks 1.
1 instruction clock cycle is 1 CPU clock cycle (f
CPU
) selected by the processor clock control register
(PCC).
Number of clock cycles is when there is a program in the internal ROM area.
n indicates the number of waits when the external memory expansion area is read.
m indicates the number of waits when the external memory expansion area is written to.
2.
3.
4.
Instruction
Group
Clock
Flag
Mnemonic
Operands
Byte
Operation
Note 1
Note 2
Z AC CY