參數(shù)資料
型號(hào): μPD780208
廠商: NEC Corp.
元件分類: 8位微控制器
英文描述: 8 Bit Single Chip Microcontrollers
中文描述: 8位單片機(jī)微控制器
文件頁數(shù): 45/78頁
文件大?。?/td> 406K
代理商: ΜPD780208
4 5
m
PD780204, 780205, 780206, 780208
DC CHARACTERISTICS (T
A
= –40 to +85 °C, V
DD
= 2.7 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
High-level
input leakage
current
I
LIH1
V
IN
= V
DD
P00 to P03, P10 to P17,
P20 to P27, P30 to P37,
P70 to P74, RESET
3
m
A
I
LIH2
X1, X2, XT1/P04, XT2
20
m
A
m
A
m
A
I
LIH3
V
IN
= 15 V
P70 to P74
80
I
LIH4
P100 to P107, P110 to P117,
V
DD
= 4.5 to 5.5 V
3
Note 1
P120 to P127 V
IN
= V
DD
3
Note 2
m
A
Low-level input
leakage
current
I
LIL1
V
IN
= 0 V
P00 to P03, P10 to P17, P20
to P27, P30 to P37, RESET
–3
m
A
I
LIL2
X1, X2, XT1/P04 XT2
–20
m
A
I
LIL3
P70 to P74
–3
Note 3
m
A
I
LIL4
P100 to P107, P110 to
P117, P120 to P127
–10
m
A
High-level output
leakage
current
Note 4
I
LOH1
V
OUT
= V
DD
P01 to P03, P10 to P17,
P20 to P27, P30 to P37,
P80 to P87, P90 to P97,
P100 to P107, P110 to
P117, P120 to P127,
FIP0 to FIP12
3
m
A
I
LOH2
V
OUT
= 15 V
P70 to P74, N-ch open-drain
80
m
A
Low-level output
leakage
current
Note 4
I
LOL1
V
OUT
= 0 V
P01 to P03, P10 to P17,
P20 to P27, P30 to P37,
P70 to P74
–3
m
A
I
LOL2
V
OUT
= V
LOAD
= V
DD
– 40 V
P80 to P87, P90 to P97,
P100 to 107, P110 to
P117,
P120 to P127,
FIP0 to FIP12
–10
m
A
Display output
current
I
OD
V
DD
= 4.5 to 5.5 V, V
OD
= V
DD
– 2 V
–15
–18
mA
Mask option
pull-up resistor
R
1
V
IN
= 0 V, P70 to P74
20
40
90
k
W
Software
R
2
V
IN
= 0 V
,
V
DD
= 4.5 to 5.5 V
15
40
90
k
W
pull-up resistor
P01 to P03, P10 to P17,
20
500
k
W
P20 to P27, P30 to P37
Notes 1.
For P110 to P117 and P120 to P127 without on-chip pull-down resistor (specifiable by mask option), a high-
level input leak current of 50
m
A (MAX.) flows only during the 1.5 clocks after an instruction has been executed
to read out ports 11, 12 (P11, P12) or port mode registers 11, 12 (PM11, PM12). Outside the period of 1.5
clocks following executing a read-out instruction, the current is 3
m
A (MAX.).
2.
For P110 to P117 and P120 to P127 without on-chip pull-down resistor (specifiable by mask option), a high-
level input leak current of 30
m
A (MAX.) flows only during the 1.5 clocks after an instruction has been executed
to read out P11, P12, PM11, and PM12. Outside the period of 1.5 clocks following executing a read-out
instruction, the current is 3
m
A (MAX.).
3.
For P70 to P74 without on-chip pull-up resistor (specifiable by mask option), a low-level input leak current
of –200
m
A (MAX.) flows only during the 1.5 clocks after an instruction has been executed to read out port
7 (P7) or port mode register 7 (PM7). Outside the period of 1.5 clocks following executing a read-out
instruction, the current is –3
m
A (MAX.).
4.
This current excludes the current which flows in the on-chip pull-up/pull-down resistor.
Remark
Unless otherwise specified, the characteritics of a shared pin are the same as those of a port pin.
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