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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
μ
PD780058Y Subseries)
(3) Register setting
The I
2
C mode setting is performed by the serial operating mode register 0 (CSIM0), the serial bus interface
control register (SBIC), and the interrupt timing specify register (SINT).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
R/W
CSIM01
0
1
1
CSIM00
×
0
1
Serial Interface Channel 0 Clock Selection
Input clock from off-chip to SCL pin
8-bit timer register 2 (TM2) output
Note 2
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
R/W
CSIM CSIM
04
0
1
CSIM PM25
02
3-wire serial I/O mode (see
17.4.2 Operation in 3-wire serial I/O mode
)
0
×
×
0
0
0
1
Note 3
Note 3
P25 PM26 P26 PM27 P27
Operation
mode
Start
bit
SI0/SB0/SDA0/
P25 pin function
SO0/SB1/SDA1/
SCK0/SCL/P27
P26 pin function
03
×
1
pin function
2-wire
serial I/O or
I
2
C bus mode
2-wire
serial I/O or
I
2
C bus mode
MSB
P25
(CMOS I/O)
SB1/SDA1
N-ch open-
drain I/O
P26
(CMOS I/O)
SCK0/SCL
N-ch open-
drain I/O
SCK0/SCL
N-ch open-
drain I/O
1
1
1
0
0
×
×
0
1
MSB
SB0/SDA0
N-ch open-
drain I/O
Note 3 Note 3
R/W
WUP
0
1
Wake-up Function Control
Note 4
Interrupt request signal generation with each serial transfer in any mode
In I
2
C bus mode, interrupt request signal is generated when the address data received after start condition
detection (when CMDD = 1) matches data in slave address register (SVA).
R
COI
0
1
Slave Address Comparison Result Flag
Note 5
Slave address register (SVA) not equal to data in serial I/O shift register 0 (SIO0)
Slave address register (SVA) equal to data in serial I/O shift register 0 (SIO0)
R/W
CSIE0
0
1
Serial Interface Channel 0 Operation Control
Stops operation.
Enables operation.
Notes 1.
Bit 6 (COI) is a read-only bit.
2.
In the I
2
C bus mode, the clock frequency is 1/16 of the clock frequency output by TO2.
3.
Can be used freely as a port.
4.
To use the wake-up function (WUP = 1), set the bit 5 (SIC) of the interrupt timing specify register
(SINT) to 1. Do not execute an instruction that writes the serial I/O shift register 0 (SIO0) while
WUP = 1.
5.
When CSIE0 = 0, COI is 0.
Remark
×
PM
××
: Port mode register
P
××
: Port output latch
: don’t care
6
5
4
3
2
1
0
7
Symbol
CSIM0
FF60H 00H
R/W
Note 1
Address After Reset R/W
CSIE0
COI
WUP
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00