
48
CHAPTER 2 OUTLINE (
μ
PD780058Y Subseries)
2.7 Outline of Function
ROM
Mask ROM
Flash memory
24 Kbytes
32 Kbytes
40 Kbytes
48 Kbytes
60 Kbytes
60 Kbytes
Note 2
High-speed RAM
1,024 bytes
Buffer RAM
32 bytes
Expansion RAM
None
1,024 bytes
1,024 bytes
Note 3
Memory space
64 Kbytes
General register
8 bits
×
8
×
4 banks
With main system clock selected
0.4
μ
s/0.8
μ
s/1.6
μ
s/3.2
μ
s/6.4
μ
s/12.8
μ
s (@ 5.0-MHz operation)
With subsystem clock selected
122
μ
s (@ 32.768-kHz operation)
Instruction set
16-bit operation
Multiply/divide (8 bits
×
8 bits, 16 bits
÷
8 bits)
Bit manipulate (set, reset, test, and boolean operation)
BCD adjust, etc.
I/O port
Total
CMOS input
CMOS I/O
N-ch open-drain I/O : 4
: 68
: 2
: 62
A/D converter
8-bit resolution
×
8 channels
D/A converter
8-bit resolution
×
2 channels
Serial interface
3-wire serial I/O/2-wire serial I/O/I
2
C bus mode selection possible : 1 channel
3-wire serial I/O mode (on-chip max. 32-byte auto transmit/receive function)
: 1 channel
3-wire serial I/O/UART mode (on-chip time-division transfer function)
selectable : 1 channel
Timer
16-bit timer/event counter
8-bit timer/event counter
Watch timer
Watchdog timer
: 1 channel
: 2 channels
: 1 channel
: 1 channel
Timer output
3: (14-bit PWM output enable: 1)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz,
2.5 MHz, 5.0 MHz (main system clock: @ 5.0-MHz operation)
32.768 kHz (subsystem clock: @ 32.768-kHz operation)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (main system clock: @ 5.0-MHz
operation)
Notes
1
. Under planning
2
. The capacities of the flash memory can be changed by using the memory switching register (IMS).
3
. The capacity of the internal expansion RAM can be changed by using the internal expansion RAM
size switching register (IXS).
μ
PD780053Y
μ
PD780054Y
μ
PD780055Y
μ
PD780056Y
μ
PD780058Y
μ
PD78F0058Y
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Item
Part Number
Internal
memory
Minimum
instruction
execution
time