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CHAPTER 23 STANDBY FUNCTION
23.2 Standby Function Operations
23.2.1 HALT mode
(1) HALT mode set and operating status
The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the
subsystem clock.
The operating status in the HALT mode is described below.
Table 23-1. HALT Mode Operating Status
Setting of HALT Mode
On Execution of HALT Instruction during Main
System Clock Operation
On Execution of HALT Instruction during
Subsystem Clock Operation
Without subsystem
clock
Note 1
With subsystem
clock
Note 2
When main system clock
continues oscillation
When main system
clock stops oscillation
Item
Clock generator
Both main system and subsystem clocks can be oscillated. Clock supply to the CPU stops
CPU
Operation stops
Port (output latch)
Status before HALT mode setting is held
16-bit timer/event counter
Operable
Operable when watch
timer output is selected
as count clock (f
XT
is
selected as count clock
of watch timer) or when
TI00 is selected
8-bit timer/event counter
Operable
Operable when TI1 or
TI2 is selected as
count clock
Watch timer
Operable when f
XX
/2
7
is
selected as count clock
Operable
Operable when f
XT
is
selected as count clock
Watchdog timer
Operable
Operation stops
A/D converter
Operable
Operation stops
D/A converter
Operable
Real-time output port
Operable
Serial interface
Other than
automatic
transmit/
receive
function
Operable
Operable when
external SCK is used
Automatic
transmit/
receive
function
Operation stops
External interrupt
request
INTP0
INTP0 is operable when clock supplied for peripheral hardware is selected
as sampling clock (f
XX
/2
5
, f
XX
/2
6
, f
XX
/2
7
)
Operation stops
INTP1 to INTP5
Operable
Bus line for
external
expansion
AD0 to AD7
High impedance
A0 to A15
Status before HALT mode setting is held
ASTB
Low level
WR, RD
High level
WAIT
High impedance
Notes 1.
Including when external clock is not supplied
2.
Including when external clock is supplied