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參數(shù)資料
| 型號： | μPD75P3018A |
| 廠商： | NEC Corp. |
| 英文描述： | 4 Bit Single Chip Microcontrollers(4位單片微控制器) |
| 中文描述： | 4位單片微控制器（4位單片微控制器） |
| 文件頁數(shù)： | 35/60頁 |
| 文件大?。?/td> | 337K |
| 代理商： | ΜPD75P3018A |
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μPD75P3018A
35
Main System Clock Oscillation Circuit Characteristics (T
A
= –40 to +85 °C, V
DD
= 1.8 to 5.5 V)
Resonator
Recommended Constants
Parameter
Conditions
MIN.
TYP.
MAX.
Unit
Ceramic
resonator
Oscillation frequency
(f
X
)
1.0
6.0
Note 2
MHz
Note 1
Oscillation
stabilization time
After V
DD
has
reached MIN. value
of oscillation voltage
range
4
ms
Note 3
Crystal
resonator
Oscillation frequency
(f
X
)
1.0
6.0
Note 2
MHz
Note 1
Oscillation
stabilization time
V
DD
= 4.5 to 5.5 V
10
ms
Note 3
30
External
clock
X1 input frequency
(f
X
)
1.0
6.0
Note 2
MHz
Note 1
X1 input high-/
low-level widths
(t
XH
, t
XL
)
83.3
500
ns
Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillation circuit
only. For the instruction execution time, refer to AC Characteristics.
2. If the oscillation frequency is 4.19 MHz < f
X
- 6.0 MHz at 1.8 V - V
DD
< 2.7 V, do not select processor clock control
register (PCC) = 0011. If PCC = 0011, one machine cycle is less than 0.95 μs, falling short of the rated value
of 0.95
m
s.
3. The oscillation stabilization time is the time required for oscillation to be stabilized after V
DD
has been applied
or STOP mode has been released.
Caution
When using the main system clock oscillation circuit, wire the portion enclosed in the broken line in
the above figure as follows to prevent adverse influence due to wiring capacitance:
Keep the wiring length as short as possible.
Do not cross the wiring with other signal lines.
Do not route the wiring in the vicinity of a line through which a high alternating current flows.
Always keep the ground point of the capacitor of the oscillation circuit at the same potential as V
Do not ground to a power supply pattern through which a high current flows.
Do not extract signals from the oscillation circuit.
DD
.
X1
X2
C1
C2
V
DD
X1
X2
C1
C2
V
DD
X1
X2
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