![](http://datasheet.mmic.net.cn/380000/-PD75F4246_datasheet_16744904/-PD75F4246_311.png)
APPENDIX C INSTRUCTION INDEX
292
AND
A, @HL ................................... 230, 258
AND
XA, rp' ..................................... 230, 258
AND
rp'1, XA ................................... 230, 258
OR
A, #n4...................................... 230, 259
OR
A, @HL ................................... 230, 259
OR
XA, rp' ..................................... 230, 259
OR
rp'1, XA ................................... 230, 259
XOR
A, #n4...................................... 230, 260
XOR
A, @HL ................................... 230, 260
XOR
XA, rp' ..................................... 230, 260
XOR
rp'1, XA ................................... 230, 260
[Accumulator instruction]
RORC
A .............................................. 231, 261
NOT
A .............................................. 231, 261
[Increment/decrement instruction]
INCS
reg ........................................... 231, 262
INCS
rp1 ........................................... 231, 262
INCS
@HL ........................................ 231, 262
INCS
mem ........................................ 231, 262
DECS
reg ........................................... 231, 262
DECS
rp'............................................. 231, 262
[Compare instruction]
SKE
reg, #n4................................... 231, 263
SKE
@HL, #n4................................ 231, 263
SKE
A, @HL ................................... 231, 263
SKE
XA, @HL ................................. 231, 263
SKE
A, reg....................................... 231, 263
SKE
XA, rp' ..................................... 231, 263
[Carry flag manipulation instruction]
SET1
CY ........................................... 231, 264
CLR1
CY ........................................... 231, 264
SKT
CY ........................................... 231, 264
NOT1
CY ........................................... 231, 264
[Memory bit manipulation instruction]
SET1
mem.bit ................................... 231, 265
SET1
fmem.bit .................................. 231, 265
SET1
pmem.@L................................ 231, 265
SET1
@H+mem.bit ........................... 231, 265
CLR1
mem.bit ................................... 231, 265
CLR1
fmem.bit .................................. 231, 265
CLR1
pmem.@L................................ 231, 265
CLR1
@H+mem.bit ........................... 231, 265
SKT
mem.bit ................................... 231, 266
SKT
fmem.bit .................................. 231, 266
SKT
pmem.@L................................ 231, 266
SKT
@H+mem.bit ........................... 231, 266
SKF
mem.bit ................................... 231, 266
SKF
fmem.bit .................................. 231, 266
SKF
pmem.@L................................ 231, 266
SKF
@H+mem.bit ........................... 231, 266
SKTCLR fmem.bit .................................. 231, 267
SKTCLR pmem.@L................................ 231, 267
SKTCLR @H+mem.bit ........................... 231, 267
AND1
CY, fmem.bit ........................... 232, 267
AND1
CY, pmem.@L ........................ 232, 267
AND1
CY, @H+mem.bit.................... 232, 267
OR1
CY, fmem.bit ........................... 232, 267
OR1
CY, pmem.@L ........................ 232, 267
OR1
CY, @H+mem.bit.................... 232, 267
XOR1
CY, fmem.bit ........................... 232, 267
XOR1
CY, pmem.@L ........................ 232, 267
XOR1
CY, @H+mem.bit.................... 232, 267
[Branch instruction]
BR
addr ......................................... 232, 268
BR
addr1 ....................................... 232, 268
BR
!addr ........................................ 232, 268
BR
$addr ....................................... 232, 268
BR
$addr1 ..................................... 232, 269
BR
PCDE ...................................... 232, 270