– ii –
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP ........................................
25
3.1
Bank Configuration of Data Memory and Addressing Mode ....................................
3.1.1
Bank configuration of data memory...................................................................................
3.1.2
Addressing mode of data memory.....................................................................................
Bank Configuration of General-Purpose Registers....................................................
Memory-Mapped I/O ........................................................................................................
25
25
27
38
43
3.2
3.3
CHAPTER 4 INTERNAL CPU FUNCTION.....................................................................................
51
4.1 Function to Select MkI and MkII Modes .........................................................................
4.1.1
Difference between MkI and MkII modes..........................................................................
4.1.2
Setting stack bank select register (SBS)...........................................................................
4.2
Program Counter (PC) ....................................................................................................
4.3
Program Memory (ROM).................................................................................................
4.4
Data Memory (RAM) ........................................................................................................
4.4.1
Configuration of data memory............................................................................................
4.4.2
Specifying bank of data memory .......................................................................................
4.5
General-Purpose Register..............................................................................................
4.6
Accumulator.....................................................................................................................
4.7
Stack Pointer (SP) and Stack Bank Select Register (SBS) .......................................
4.8
Program Status Word (PSW) .........................................................................................
4.9
Bank Select Register (BS)..............................................................................................
51
51
52
53
54
59
59
60
64
65
65
69
73
CHAPTER 5 PERIPHERAL HARDWARE FUNCTION..................................................................
75
5.1
Digital I/O Port .................................................................................................................
5.1.1
Types, features, and configurations of digital I/O ports ...................................................
5.1.2
Setting I/O mode.................................................................................................................
5.1.3
Digital I/O port manipulation instruction ............................................................................
5.1.4
Operation of digital I/O port................................................................................................
5.1.5
Connecting pull-up resistor ................................................................................................
5.1.6
I/O timing of digital I/O port................................................................................................
Clock Generation Circuit................................................................................................
5.2.1
Configuration of clock generation circuit ...........................................................................
5.2.2
Function and operation of clock generation circuit...........................................................
5.2.3
Setting system clock and CPU clock.................................................................................
5.2.4
Clock output circuit .............................................................................................................
Basic Interval Timer/Watchdog Timer ..........................................................................
5.3.1
Configuration of basic interval timer/watchdog timer........................................................
5.3.2
Basic interval timer mode register (BTM)..........................................................................
5.3.3
Watchdog timer enable flag (WDTM) ................................................................................
5.3.4
Operation as basic interval timer .......................................................................................
5.3.5
Operation as watchdog timer .............................................................................................
5.3.6
Other functions ...................................................................................................................
Watch Timer .....................................................................................................................
5.4.1
Configuration of watch timer ..............................................................................................
5.4.2
Watch mode register ..........................................................................................................
75
76
80
82
85
87
88
90
90
91
102
104
107
107
107
109
109
110
112
114
115
116
5.2
5.3
5.4