
CHAPTER 5 PERIPHERAL HARDWARE FUNCTION
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(2) Serial bus interface control register (SBIC)
Fig. 5-60 shows the format of the serial bus interface control register (SBIC).
SBIC is an 8-bit register that consists of bits that control the serial bus and flags that indicate the status of
the data input from the serial bus.
This register is manipulated by a bit manipulation instruction. It cannot be manipulated by a 4- or 8-bit memory
manipulation instruction.
Some bits of this register can only be read, and some can only be written (refer to
Fig. 5-60
).
All the bits are cleared to 0 when the RESET signal is asserted.
Caution
Only the following bits can be used in the three-line and two-line serial I/O modes:
Bus release trigger bit (RELT) .....Sets SO latch
Command trigger bit (CMDT) .......Clears SO latch
Fig. 5-60 Format of Serial Bus Interface Control Register (SBIC) (1/3)
Remarks 1.
(R)
(W)
(R/W) : read/write
: read only
: write only
2.
3.
7
6
5
4
3
2
1
0
RELT
CMDD RELD
CMDT
ACKT
ACKE
ACKD
BSYE
Address
SBIC
FE2H
Symbol
Bus release trigger bit (W)
Command trigger bit (W)
Bus release detection flag (R)
Command detection flag (R)
Acknowledge trigger bit (W)
Acknowledge enable bit (R/W)
Acknowledge detection flag (R)
Busy enable bit (R/W)